Cyclone IV GX ALTLVDS_RX

[Gauthier_Auvray]

Hi, In a project we use ALTLVDS_RX (9 channels, de-serialization factor=6) in a Cyclone IV GX FPGA. If my understanding is correct: - SERDES is implemented in LE (with DDIO) - DPA is not available for this family - SDC constraints are required on the interface I made a simple design with just the ALTLVDS_RX (PLL inside). Data rate is 720Mbps, clock rate is 360MHz (data transmitted in DDR mode), datas are center aligned so I configure phase clock to 0°. I added input delay constraints in the SDC based on the Tco min/max provided by the datasheet of the component that interfaces to the SERDES. During compilation I get those warnings: Warning (176441): The I/O pin ads_data[0] cannot meet the timing constraints due to conflicting requirements. The I/O pin is a PLL compensated I/O, but the setup/hold requirements are in conflict with the source PLL mode(source synchronous or ZDB). Can anyone explains? Best regards, Gauthier

[AqidAyman_Intel]

Hello Gauthier,

Thank you for reaching out Intel FPGA Community.

I would like to recommend you check on this Knowledge Base article published regarding the error. You can refer to this link:

Warning (176441): The I/O pin < pin name > cannot meet the... (intel.com)

There is also community discussion that was similar on the error seen by you. Refer here:

Solved: Warning (176441): The I/O pin <name> cannot meet the timing constraints due to conflicting require - Intel Communities

I hope it helps you a bit.

Regards,

Aqid

[AqidAyman_Intel]

As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.