Cyclone IV GX LVDS clock input resistor termination

[Altera_Forum]

Hi Altera experts, 

 I am designing using the EP4CGX15BF14C8 (I have the transceiver dev board to try my design).  Question I want a reference clock for the transceivers so I use a 125Mhz oscillator which is LVDS and I connect to the dedicated clock inputs (diff clock 7 p & n pins J6 and J7). Do I need a termination resistor? Or can the FPGA terminate?  Also if I use this clock for the transciever do I have to use 2.5V as power supply for the IOBANK 3A ?  Thanks

[Altera_Forum]

You need a termination resistor (see page 6-22 of the handbook):The LVDS standard does not require an input reference voltage, but it does require a 

100- termination resistor between the two signals at the input buffer. An external resistor network is required on the transmitter side for the top and bottom I/O banks. page 6-28The LVDS receiver requires an external 100- termination resistor between the two signals at the input buffer. table 6-10 (volume 1) and table 1-5 (volume 2) VCC_CLKIN for LVDS = 2.5V Good luck, Ton

[Altera_Forum]

Thanks for the reply Ton, 

 I guess it addresses some of my concerns but since I wish to use the 125Mhz for the transceivers don't I have to coinsider it a REFCLK. In volume 2 of the device handbook 1-22 there is a table of supported standards. It seems LVDS has to be AC coupled with off chip termination that also needs to restore the the Vcm. But here is the rub, the reference board I have 'Cyclone IV GX Transceiver starter kit' does not have AC coupling, it has DC from a LVDS clock with just the off chip terminator. So which is correct the device handbook or the starter kit?  Still have a dilemma  Dave

[Altera_Forum]

Hi Dave, 

 LVDS doesn't have te be AC coupled. Check the handbook volume 1 page 6-33. This is not about LVDS and not about REFCLK, but I'm sure this scheme also works for LVDS @ REFCLK.  See also volume 2 table 1-2 and the text below. LVDS coupling can be DC. Just keep the common mode voltage below 0.82V. If you can guarantee that, I'm pretty sure it will work.  Good luck, Ton

[Altera_Forum]

Looking carefully at the schematic of the Cyclone GX transceiver starter kit the ref clock that is LVDS is AC coupled and terminated off chip. But then there does not seem to be any attempt to restore the DC level (see c4gx_pcie_revb.pdf pages 5 & 6). 

 I guess if I copy this schematic I will not go far wrong.

[Altera_Forum]

I don't have access to c4gx_pcie_revb.pdf at this moment. My ftp doesn't work. So if you are willing to email it to me or post it, I can have a look. 

 If you are going to implement the AC-coupled version, you can alway replace the capacitors with 0 Ohm resistors. It will affect your line characteristics, though.  But be sure to use the 100 Ohm (or 2x 50 Ohm) termination. That's absolutely necessary.  Success, Ton

[Altera_Forum]

The GxB reference clock input have HCSL standard, not usual LVDS. That's basically the same with all Altera Gigabir receivers. They need AC coupling for LVDS.  

 The termination implemented in DevKit, both for PCIE originated RefClk (HCSL standard) as well as internal generated crystal clock (LVDS standard) is not according to the suggestions in the hardware manual (Fig. 1-22 respectively 1-23). I'm not using Cyclone IV GX yet and can't tell, if it can work reliabably, though. If you are designing a new board, you may want to file a support request before.  P.S.: I think it would be safe to provide the termination suggested in the hardware handbook in both cases. Rs is usually set to 0 with common PC motherboards.

[Altera_Forum]

Hi, 

I have the same concern about the PCIe refclk termination and coupling. We are using the cyclone-IV GX device with 4x PCI express. Earlier for xilinx part, we have used LVDS standard for REFCLK and it was ok. For altera the refclk reciver is HCSL standard ?.   Thanks Sharan

[Altera_Forum]

The suggested REFCLK interface can be found in the Cyclone IV hardware manual under table 1–5. refclk i/o standard support and Figure 1-22 and 1-23.