Hi all!I designed a board with PCIE interface and implemented it on Cyclone IV GX (EP4CGX15BN11C8N). However, the board does not work as it should, it is not even determined by the BIOS. For debugging, I took a working project (chaining_dma) from Cyclone IV GX Transceiver Starter Kit, changed the chip to my (EP4CGX15BN11C8N) and did the following tests: 1. RefClk turned on the LED, it flashes as it should. ( 100/(2**26) Mhz) 2. PERST# signal resets the logic, as it should (checked in SignalTap) 3. LTSSM switches state00000 (detect.quiet) -> state00001 (detect.active) -> state00000 (detect.quiet) -> state00001 (detect.active) ->... 4. test_out bus is always 0000002003100000h. In my opinion, everything indicates the inoperability of the lanes (rx_in and/or tx_out). Can I do any additional helpful tests? Is there any possibility that the problem is not on the board side? I used GXB0 block and refclk1 (not refclk0) input - сan be a problem with this? Perhaps the problem is the noise in the power supply of the transceivers? Any suggestions? PS. PCIe traced through the M.2 connector, the rx and tx lanes have an impedance of 85 ohms (controlled at factory) and 1/2 inch length . I have no idea, why this short lanes with controlled impedance do not working... Thanks!
- Cyclone® IV FPGAs
I had unused output pins in my design that were left unspecified. I added the extra effort option the fitter and these pins were set to output pin on the SMBus lines on the PCIe interface.
We found our problem, it was to do with the large size (256MB) of the BAR 0 register, apparently some BIOS don't like it.
Here is the question/answer in case anyone is having similar issues: https://forums.intel.com/s/question/0D70P000006QtndSAC