I am looking to do some SEU testing using the built-in CRC function on the Cyclone IV (as described in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51009.pdf )
Is there information on what the minimum supporting circuitry that is required to get this to work, as well as instructions on how to activate this and monitor using the Quartus software?
You may refer to https://www.intel.fr/content/dam/www/programmable/us/en/pdfs/literature/an/an357.pdf for more information on the timing.
In order to enable it you need to include the "cycloneiv_crcblock" on your FPGA design. If you only need to monitor the CRC Error then you can just enable it on your Quartus Project.