HalloSo we have a DE0-NANO board with Cyclone IV E FPGA (EP4CE22F17C8). As it is mentioned everywhere that 8 means the highest speed grade. For our design we need a Fmax of 50 MHz, which i can achieve with my current design and Speed grade 8 FPGA. When when chose the same FPGA with a spped grade of 6, then the Fmax falls down to 40 MHz, is it possible to lift up the Fmax to 50 MHz, by changing the paths which fail the timing and introducing pipe-lining or its a restriction from the speed grade? From the Quatras Time Quest Analyzer i have figured out the paths with the worst timing and they have a long computational logic, if i change my design and add pipe-lining would it be enough to get the Fmax back upto 50 MHz again?
Hi, For example, a Cyclone device with a -6 speed grade has a delay of 6 ns through a LUT's. Devices with low speed grade numbers run faster than devices with high speed grade numbers. Yes you can achieve 50 MHz. I/O standards such as 3.3, 3.0, 2.5, 1.8, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency with a 10 pF load. Actual achievable frequency depends on design- and system-specific factors. Perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)