Cyclone IV/V Transceiver IO Standard | Biasing | Termination | PCIe

[Altera_Forum]

Hello, 

I have a fundamental question regarding the transceivers of Cyclone IV/V devices. The documentation says, that these transceivers support 'PCML-1.5V IO STANDARD' for TX lanes.  https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-53001.pdf  Follwoing documentation explains the use of the transceivers: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-52001.pdf  It says, that the transceivers are "current-mode drivers" which is contrary to PCML because PCML is Pseudo!!!-CML and not true CML.  The problem I see with this is following: It says you should disable on Chip termination for PCIe applications (85Ohm). In every design I found online the PCIe lanes are AC coupled with a capacitor and connected directly to the FPGA. However, the docuentation states, that the transceivers MUST be biased externally if no on-chip termination is selected (required for PCIe).  I do not see these biasing resistors in the schematic of any PCIe hardware.  Can anyone explain to me, how this works? The datasheet explicitly says, that the Transceiver outputs are current mode drivers...  Furthermore the transceiver manual says: - Output voltage swing can be configured - Output voltage swing is dependent on termination resistor, due to current mode drivers.  Can anyone clarify these contradictory statements?  I searched the internet, but nobody really explains the Hardware aspect of the transceivers and how to properly connect them.

[Altera_Forum]

As you've stated - PCML is Pseudo CML. Altera can't call it CML because the construction of the I/O cell is not a true CML design. However, Altera's PCML ensures the behaviour of the I/O cell is appropriate for connection to a true CML device. It is a 'current-mode drive'. 

 I recommend you download the documentation and schematics for one of Altera's PCIe based development cards. This will clarify how they connect up an FPGA to a PCIe lane. You won't find any biasing resistors, only tx ac coupling caps.  Cheers, Alex

[Altera_Forum]

The manual for the transceivershere (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-52001.pdf) says on 1-14: 

 disable oct to use external termination if the link requires a 85 ohm termination, such as when you are interfacing with certain pcie gen1 or gen2 capable devices.  On top of that there is: if you disable the oct, then you must externally terminate and bias the receiver. ac-coupled links are required for pcie (...)  The problem is: I don't care if it works with just AC coupling caps (and I know that it does). I need an official source that states that this way of wiring PCIe is correct and supported. Unfortunately the document (as written above) states, that an external termination is used for PCIe. I won't be able to justify a circuit design that contradicts with the manual.  The manual clearly says: 1. Disable internal Termination (OCT) for PCIe 2. Transceivers must be biased externally if internal termination is disabled  If I get something really wrong here, please tell me. Otherwise I must refrain from using an Altera chip in my current project. The current development is done on a Terasic Dev-Board and works with just AC coupling and disabled OCT. But it contradicts with the manual and therefore I won't be able to justify this design in front og my higher-ups.