Cyclone LUT Performance

[Altera_Forum]

Hey, 

 How can I get LUT performances in various Altera FPGAs, or specifically at Cyclone 3?   Thanks

[Altera_Forum]

--- Quote Start ---  Hey,  How can I get LUT performances in various Altera FPGAs, or specifically at Cyclone 3?   Thanks  --- Quote End ---    Hi,  what do you mean with "LUT" performance ?   Kind regards  GPK

[Altera_Forum]

Hey,  

 I meant the LUTs Propagation delay.  Thanks.

[Altera_Forum]

--- Quote Start ---  Hey,   I meant the LUTs Propagation delay.  Thanks.  --- Quote End ---    Hi,  I assume you would like to know how fast your design could run in a FPGA ? Keep in mind that the LUT delay is only one part of delay. The other part is the routing delay, which is more important in newer FPGA's. Also some parts of your design could be implemented in e.g. DSP block ( Multiplier ...). The best way to find out how fast your design will run is to  run the Synthesis and P&R with Quartus.  Kind regards  GPK

[Altera_Forum]

The closest thing you're going to get to a documented number is the Core Performance specifications from the Cyclone III datasheet: 

 http://www.altera.com/literature/hb/cyc3/cyc3_ciii52001.pdf  Pletz is correct. You really need to compile your design and see how it performs.  Jake

[Altera_Forum]

First thing first, Thank you for the help. 

 Now, My goal isn't to check how fast my design should work, but to plan my algorithms so they will be able to work at certain frequency, while trying to work with maximum number of logic levels.  If you got an idea how it could be made, I would be glad to hear.  Thanks again for the help.

[Altera_Forum]

--- Quote Start ---  First thing first, Thank you for the help.  Now, My goal isn't to check how fast my design should work, but to plan my algorithms so they will be able to work at certain frequency, while trying to work with maximum number of logic levels.  If you got an idea how it could be made, I would be glad to hear.  Thanks again for the help.  --- Quote End ---    Hi rishum,  in my point of view there is no way to get your required information without a P&R run. Of coarse you can calculate the delay of nxLUT delay, but you don't know how your functions will be implemented. Are DSP blocks used? How is routing delay ? Which speed grade is used ....  Kind regards  GPK