Cyclone PLL frequency range

[Altera_Forum]

I’m currently working on project which uses Cyclone Family Part#EP1C20F400I7. Device has internal PLL and I’m using Altera’s megafunction “altpll” component to simulate logic. The device has been configured for a design and I must now attempt to drive it from another source. 

 External Device generates 80Mhz clock to supply clock for FPGA. The FPGA uses the internal PLL to sync an external clock signal to generate an internal clock signal for core logic. During simulation utilizing the mega-function, the device is shown to not respond to lower frequencies than that which is specified as the nominal frequency for the PLL. Is this a model limitation or a hardware limitation?   My question is, if I supply clock with frequency of 50Khz(or less) through external device on real physical hardware, would the internal PLL be still able to generate output signal?    What is the minimum clock frequency that the PLL can handle?

[Altera_Forum]

If you supply reference clock different from what you set in the altpll, the PLL might not able to lock to the reference clock. You can try to update the settings in the altpll to take in lower reference clock frequency.

[Altera_Forum]

As for the minimum frequency, you can check the Cycone datasheet. As I look at the doc, it seems like minimum is 15.625MHz which is some distance from your kHz requirement.