Cyclone V 5CEFA4F23C8 has 24 DQ pins for LPDDR2 Hard Memory Interface

[Altera_Forum]

Hi. 

 I am using the 5CEFA4F23C8 and LPDDR2 in a design, and I want to use the Hard Memory Interface for LPDDR2.  I've noticed that the LPDDR2 hard interface has 24 dedicated DQ pins. That seems to me like such an odd number, because afaik LPDDR2 only comes in x16 and x32 configurations, and Qsys won't let me configure the UniPHY LPDDR2 as 24-bit either.  So why 24 DQ pins? Can I somehow use this interface for more than x16? Can I use it for x32?  If I only use the hard interface for x16, can I use the last 8 DQ pins for other purposes, or are they reserved for the hard memory interface?

[Altera_Forum]

It does seem to be a strange number for DDR interface. As I understand it though, if you use the HMC at x16 then you should be able to use the unused pins for other purposes, but note that they will have I/O voltage of your LPDDR2 interface. 

 I think the point for the x24 is if you enable ECC.

[Altera_Forum]

I think you are right, I read up on ECC in HMC/EMI documentation, and an additional 8 bits are needed for ECC. And now I was able to instantiate a 24-bit LPDDR2 UniPHY interface in Qsys when I turned on ECC. 

 So thank you very much for your reply, now I know why the interface is 24-bits, and if I ever need ECC I know what to do :)

[Altera_Forum]

Hello, as far as I know you can use all of 24 DQ pins for your data. You should turn on USER ECC(manual ECC). It can be instantiated in Quartus for example for 5CGXFC5C6 fpga. 

 Alex.