We use the Cyclone V "5CEFA7U19A7N" on a PCB with a 25MHz clock, which is redundantly driven on two PINS of the FPGA (same oscillator).
The clock is fed by a MEMS oscillator via a hardware clock buffer.
The problem is that not all 7 PLLs are locked, but mostly only one. If the PCB (mainly the FPGA) is warmed up the PLLs will lock one after the other. The same behaviour, but other way around (losing the PLL locked signal one by one) occurs during cool down of the PCB.
A dependency on a certain clock of the hardware clock buffer could not be found so far.
Are there any known manufacturing problems or software programming issues that can cause such a problem?
Is there any possibility to figure out the root cause of the issue?
I am open for further questions to solve the problem.
From your description, are you using 2 dedicated clock pins as refclk to 7 PLLs?
What is the temperature when we referring to warm up and cool down? How did you warm up or cool down the board? How do you narrow down the issue is on the PLL itself when the PCB is warming up and cooling down, as the board has multiple components, have we check if the failure is not on the clock source or components like regulator?
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