Cyclone V: Communication with EPCQ Device in User Mode after Bootup

[Altera_Forum]

For my design, I'm using the Cyclone V (5CEFA7F23). I'm looking to boot the "factory image" from an EPCQ flash device using Active Serial x4, and then from the factory image (when in user mode), communicate with the same EPCQ device. The Cyclone V device will be receiving a firmware update over Ethernet that I'm looking to write to the flash device. I see within pin planner that the data pins are not assignable, which i presume is because they are dedicated for boot. For example, AS_DATA0 or pin AB4, is not assignable.  

 Is there a way to communicate with the flash device using the same pins that are used for boot? Or do i have to communicate in user mode via additional standard I/O pins? If the latter, I imagine the dedicated boot data[3:0] pins go into high-z, but I don't see this mentioned in the documentation.   Can someone provide any insight into this?  Thx

[Altera_Forum]

The EPCS Serial Flash Controller Core also works with EPCQ but (currently?) only in x1 mode. They call it "EPCS/EPCQx1 Serial Flash Controller" 

 http://www.altera.com/literature/ug/ug_embedded_ip.pdf

[Altera_Forum]

Did you ever resolve this issue? I am having this issue as well. It seems like the tool is not allowing me to assign these pins as user I/O after config as was possible in previous device families.

[Altera_Forum]

I have recently been doing the same thing, and according to Altera it is not possible to use these pins directly in user mode.  

However, the ALTASMI_PARALLEL IP can be used to access the flash.   In my opinion, ALTASMI_PARALLEL has a lot of weaknesses:  

• It does not have a working simulation model. 
• It is not well documented what is happening on the interface towards the flash. 
• We found a problem with the sector erase command (which is supposed to be fixed in 13.1) 

  For these reasons, we desided to make a new revision of the board and connect these pins in parallel to standard IO pins. We then used our own hdl module to control the flash. This works perfectly, but you have to remember to check the "Enable input tri-state on active configuration pins in user mode"

[Altera_Forum]

--- Quote Start ---  I have recently been doing the same thing, and according to Altera it is not possible to use these pins directly in user mode.  However, the ALTASMI_PARALLEL IP can be used to access the flash.   In my opinion, ALTASMI_PARALLEL has a lot of weaknesses:  

• It does not have a working simulation model. 
• It is not well documented what is happening on the interface towards the flash. 
• We found a problem with the sector erase command (which is supposed to be fixed in 13.1) 

  For these reasons, we desided to make a new revision of the board and connect these pins in parallel to standard IO pins. We then used our own hdl module to control the flash. This works perfectly, but you have to remember to check the "Enable input tri-state on active configuration pins in user mode"  --- Quote End ---    Thanks for the input. This is the info I needed.

[Altera_Forum]

I'll also add that the ALTASMI_PARALLEL block is just far too complicated for may uses. 

All you need is a simple block to allow an Avalon master to bit-bang the interface. The most would be something to allow 32bit and 8bit reads/writes to be done an a single Avalon cycle. Everything else can be done with a very simple software interface - not based on the HAL code for the old EPCS flash controller which is a lot of library code that doesn't expose the interfaces the code needs.