Cyclone V: Dynamic phase shift

[Mikexx]

I am implementing this using the PLL Intel FPGA Megafunction (ALTERA_PLL)

Is this the best IP to use where I wish to adjust phase relationships?

I can't find any documentation to suggest the phase shift for a single increment using the ports:

phase_en
scanclk
updn
cntsel
phase_done

but trial and practice suggests it's 64 increments for 360 degrees.

Is there any formal specification for a phase shift increment ? I've searched and can't find any detail in the Cyclone V documentation but presume there's a document I haven't come across?

[FvM]

Hi,
consider the relation between dynamical and programmable phase shift. Both have the same phase resolution. Review respective handbook paragraph:
"Programmable Phase Shift

The programmable phase shift feature allows the PLLs to generate output clocks with a fixed phase offset.
The VCO frequency of the PLL determines the precision of the phase shift. The minimum phase shift
increment is 1/8 of the VCO period. For example, if a PLL operates with a VCO frequency of 1000 MHz,
phase shift steps of 125 ps are possible.
The Intel Quartus Prime software automatically adjusts the VCO frequency according to the user-specified
phase shift values entered into the IP core."

Getting 360° phase shift in 64 steps means that output frequency is 1/8 of vco frequency.

Regards
Frank

[Mikexx]

Many thanks for your reply.

I can see that with a VCO frequency of 1000MHz and a phase shift of 125ps this will give an increment of 1/8 of the VCO period., Such that phase shifts would be incremented of 45 degrees.

I don't understand the phrase "The Intel Quartus Prime software automatically adjusts the VCO frequency according to the user-specified phase shift values entered into the IP core." I thought the frequency is set by "Desired Frequency" in the MegaWizard Plugin Manager where I can also introduce an initial phase shift, or delay.
 

However, in my case I have a 50MHz reference clock and 50MHz output clocks. I can confirm the frequency is independent of the phase shift I introduce using the port signals mentioned in my OP.

On closer inspection I believe there might be a total of 72 increments to implement 360 degrees. However I don't understand, "Getting 360° phase shift in 64 steps means that output frequency is 1/8 of vco frequency." The VCO frequency is 50MHz and the output frequency is also 50MHz, independent of the phase shift I introduce.

I still can't see where or understand how I can predict the phase shift for a phase increment.

[FvM]

Hi,

phase step resolution is 45°*Fout/Fvco.

If the PLL configuration tool is free to vary vco frequency, the phase step setting will be considered. But often vco frequency is already fixed by output frequency parameters, in so far the respective statement in device handbook can be misleading.

Regards
Frank 

[Mikexx]

Thanks for the reply.

Although the input and output frequencies are both 50MHz, I can see under "Advanced Parameters" the "PLL Output VCO Frequency" is "300.0 MHz".

So I assume from that there should be 48 steps.

[FvM]

Hi,
you find the phase step information for all PLL outputs in compilation report/fitter/resource section/PLL usage

[Mikexx]

Many thanks, I can confirm the PLL Usage Summary does say the PLL VCO Frequency is 300MHz.

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