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Altera_Forum
Honored Contributor I
1,563 Views

Cyclone V E Development Kit failed on Active Serial Configuration via JTAG

Hi All,  

I am currently working on Cyclone V E Development Kit. I tried to save configuration file into EPCQ256SI16N. I did follow the youtube https://www.youtube.com/watch?v=dpsfcgnqocu to generate .jic file. I set up MSEL[4-0] pin is  

MSEL 4 : 1 

MSEL 2: 0 

MSEL 1: 1 

MSEl 0: 0 

 

as shown in Table 7-2: MSEL Pin Settings for Each Configuration Scheme of Cyclone V Devices of Cyclone V Handbook Device. But I am still get programmer process failed around 80 and 90%. I used Quartus 13.1 service pack 1. On the Quartus, it shows error "Can't recognize silicon ID for device 1" 

 

Does anyone have any ideas what happens on it? Thanks.
0 Kudos
19 Replies
Altera_Forum
Honored Contributor I
317 Views

Hi Jhon, 

 

You may be receiving this error if you have 2 programming headers (JTAG and Active Serial (AS)) on your board and are trying to program the EPCS device directly but are connected to the JTAG header. If you are directly programming the EPCS device you will need to make sure you have the programming cable connected to the AS programming header. 

 

You also may get this error if you have a noisy TCK signal or if the JTAG or AS header are not powered with the correct voltage. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

Altera_Forum
Honored Contributor I
317 Views

Hi, 

 

Make sure the jumpers shown below are configured in the factory default settings: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=14406  

https://www.alteraforum.com/forum/attachment.php?attachmentid=14407  

https://www.alteraforum.com/forum/attachment.php?attachmentid=14408  

https://www.alteraforum.com/forum/attachment.php?attachmentid=14409  

 

Put these DIP switches in the factory defaults as shown above and then try configuring the FPGA. It should work.
Altera_Forum
Honored Contributor I
317 Views

 

--- Quote Start ---  

Hi Jhon, 

 

You may be receiving this error if you have 2 programming headers (JTAG and Active Serial (AS)) on your board and are trying to program the EPCS device directly but are connected to the JTAG header. If you are directly programming the EPCS device you will need to make sure you have the programming cable connected to the AS programming header. 

 

You also may get this error if you have a noisy TCK signal or if the JTAG or AS header are not powered with the correct voltage. 

 

 

--- Quote End ---  

 

 

I did indirect programing using .jic file. I use development board kit. I do not design PCB board for FPGA.
Altera_Forum
Honored Contributor I
317 Views

 

--- Quote Start ---  

Hi, 

 

Make sure the jumpers shown below are configured in the factory default settings: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=14406  

https://www.alteraforum.com/forum/attachment.php?attachmentid=14407  

https://www.alteraforum.com/forum/attachment.php?attachmentid=14408  

https://www.alteraforum.com/forum/attachment.php?attachmentid=14409  

 

Put these DIP switches in the factory defaults as shown above and then try configuring the FPGA. It should work. 

--- Quote End ---  

 

 

Follow the reference manual for development board kit, the factory default setting is for FPP Configuration, it's not for AS configuration. I have tried all combination of MSEL[4-0], it doesn't work for any combination setting.
Altera_Forum
Honored Contributor I
317 Views

1. Yes, all steps in youtube you followed is correct, just need change the option epcs128 to epcq256

2. Wrong, cyclone v and cyclone v e have different handbook, and you are referring https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cyclone5_han... 

pg239 table 7-2 is Cyclone V. 

2a. Correct handbook for Cyclone V E is https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_cve_fpga_dev_kit.pd.... Refer pg12 and pg13 for your msel pin. They involve only 4 MSEL switches for sw1(MSEL) + sw2(JTAG chain) + sw3(user dip) + sw4(board setting) 

3. "Can't recognize silicon ID for device 1" means you choosing EPCS instead of EPCQ. Please take note. 

4. Correct, you are using JTAG and serial configuration, default MSEL is FPP, therefore cannot use default dip switch. 

5. SW1 you will confuse because handbook not provided the serial configuration pin, you may refer schematic which is inside the kit as zip in https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-e.html. I hereby summarize for easier option. 

5a. MSEL0=connected to T8 pin=ddr3 or Max V. Example MSEL0=1=Off=disable connection to Max V and DDR3. 

MSEL1=connected to P9 pin=ddr3 or Max V. 

MSEL2=connected to G5 pin=Flash P30(for parallel memory) or Max V or Max II power or uC 

MSEL4=connected to M7 pin=ddr3 or or Max V 

DDR3=U7(look on your board labeled)=JTAG blaster TDI 

W9 pin=TDO of JTAG. 

5b. If you are using EPCQ256 and JTAG, sw1 shall be somewhere 0010 through Max V and resistor rework or 1111 bypass Max V and resistor rework, for sw2 3 4, please study it correctly, fan on/off or Max V enable/disable or etc, everything is there in handbook pg12 pg13 given. 

 

Edited link missing, the method to post link upgraded during I post this. 

 

Best Regards, 

Tzi Khang, Lim 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
317 Views

 

--- Quote Start ---  

1. Yes, all steps in youtube you followed is correct, just need change the option epcs128 to epcq256

2. Wrong, cyclone v and cyclone v e have different handbook, and you are referring https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cyclone5_han... 

pg239 table 7-2 is Cyclone V. 

2a. Correct handbook for Cyclone V E is https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_cve_fpga_dev_kit.pd.... Refer pg12 and pg13 for your msel pin. They involve only 4 MSEL switches for sw1(MSEL) + sw2(JTAG chain) + sw3(user dip) + sw4(board setting) 

3. "Can't recognize silicon ID for device 1" means you choosing EPCS instead of EPCQ. Please take note. 

4. Correct, you are using JTAG and serial configuration, default MSEL is FPP, therefore cannot use default dip switch. 

5. SW1 you will confuse because handbook not provided the serial configuration pin, you may refer schematic which is inside the kit as zip in https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-e.html. I hereby summarize for easier option. 

5a. MSEL0=connected to T8 pin=ddr3 or Max V. Example MSEL0=1=Off=disable connection to Max V and DDR3. 

MSEL1=connected to P9 pin=ddr3 or Max V. 

MSEL2=connected to G5 pin=Flash P30(for parallel memory) or Max V or Max II power or uC 

MSEL4=connected to M7 pin=ddr3 or or Max V 

DDR3=U7(look on your board labeled)=JTAG blaster TDI 

W9 pin=TDO of JTAG. 

5b. If you are using EPCQ256 and JTAG, sw1 shall be somewhere 0010 through Max V and resistor rework, for sw2 3 4, please study it correctly, everything is there in handbook pg12 pg13 given. 

 

Edited link missing, the method to post link upgraded during I post this. 

 

Best Regards, 

Tzi Khang, Lim 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

Hi @Tzi Khang,  

Your info makes me more confusing. The link https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_cve_fpga_dev_kit.pd... is the user guide of Cyclone V E Development Kit, it's not handbook. In this guide, it doesn't talk much about how to set up MSEL. I have tried MSEL[4-0] 0010 but it failed at 99% or 98%. It drives me nut.  

I selected EQCQ256 in Device and Pin option. Have you tried your method on Cyclone V E Development board and get it compile successfully? I am newbie, so I don't know much about this process.
Altera_Forum
Honored Contributor I
317 Views

Using dev kit, just refer to the given user guide and manual and schematic you will be fine. Do not go and look for Cyclone V handbook, it makes you confuse. 

https://www.alteraforum.com/forum/attachment.php?attachmentid=14417  

Resistor rework means, please go and find 1k resistor and put to them connected to Vccpgm. 

Since you are beginner, use the 1111 and bypass Max V configuration. 

 

Best Regards, 

Tzi Khang, Lim 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
317 Views

 

--- Quote Start ---  

Using dev kit, just refer to the given user guide and manual and schematic you will be fine. Do not go and look for Cyclone V handbook, it makes you confuse. 

https://alteraforum.com/forum/attachment.php?attachmentid=14417&stc=1  

Resistor rework means, please go and find 1k resistor and put to them connected to Vccpgm. 

Since you are beginner, use the 1111 and bypass Max V configuration. 

 

Best Regards, 

Tzi Khang, Lim 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

I don't understand "please go and find 1k resistor and put to them connected to Vccpgm". What do you mean about it? Does it mean that I just need to change the Sw1 combination. I have tried combination "1111", but it doesn't work. Is there any other thing I missing in configuration process? If you are successful to program it, what MSEL combination did you use?
Altera_Forum
Honored Contributor I
317 Views

Hi John. 

1. Make sure there are these three documents, schematic="C5E_DEV_KIT_B", Userguide="ug_cve_fpga_dev_kit", Manual="rm_cve_fpga_dev_board". 

2. By default, this board support Fast Passive Parallel(FPP), sw1 from MSEL0 until MSEL4 equate to 0000. 0 means it is grounded, understand the schematic, it is at pg8 of schematic. 

https://alteraforum.com/forum/attachment.php?attachmentid=14431&stc=1  

3. Why set 0000 at FPP which is default? 

Kindly study and understand, an example of one of the MSEL switch is given: 

Referring MSEL2 set to 0, it is using Flash. Flash(P30) means parallel programming. EEPROM(EPCS or EPCQ) means serial programming. This is the naming system, Flash=parallel, EEPROM=serial. Similarly, info MSEL0 is connected to MAX V can be found and so on. 

4. Look at "rm_cve_fpga_dev_board" pg23, program using EPCQ, original text from that page has given the info, "In order to set the configuration scheme to AS mode, resistor rework needs to be done." Resistor rework=add resistor to the 3.3V that are applied to the MSEL0 till MSEL4 when dip switch is at 1111. 

4a. This means user have to change the original grounded MSEL0 until MSEL4 into powered by 3.3V Vccpgm, but do not connect 3.3V directly and must connect 1kohm resistor to it. Use the breadboard to connect the 1kohm resistor. From basic electronics, that 1kohm is used to lower the current flow and help dispense heat in FPGA. 

4b. This is simplified as it can be, do not skip resistor and direct put 3.3V to MSEL, it will damage the board through high current inrush, in this modifying case, it is not recommended for new learner unless user know how to modify connection. 

 

 

Last edited to grammar, remove all personal pronouns(I, You, We, They, etc), and picture into attachment. 

 

 

Best Regards, 

Tzi Khang, Lim 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
317 Views

Hi John, 

 

Please refer to the following manual for the Cyclone V E Dev Kit :  

 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/rm_cve_fpga_dev_bo... 

 

The following is taken from the Cyclone V E kit manual: 

 

--- Quote Start ---  

 

By default, this board has a FPP configuration scheme setting. In order to set the configuration scheme to AS mode, resistor rework needs to be done.  

Configure the MSEL setting using the MSEL DIP switch (SW1) to change the configuration scheme.  

 

--- Quote End ---  

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=14427  

 

What this means is that, to use EPCQ device , you may have to rework the board with 10K resistors as shown in the figure. Before proceeding , please check your board if this configuration is already present. If so, then you just need to modify the SW settings and try. If not, then you need to get 10K resistors and wire the respective signals as shown in the schematic, change the SW settings and then try. 

 

-Abr
Altera_Forum
Honored Contributor I
317 Views

 

--- Quote Start ---  

Hi John. 

1. Make sure there are these three documents, schematic="C5E_DEV_KIT_B", Userguide="ug_cve_fpga_dev_kit", Manual="rm_cve_fpga_dev_board". 

2. By default, this board support Fast Passive Parallel(FPP), sw1 from MSEL0 until MSEL4 equate to 0000. 0 means it is grounded, understand the schematic, it is at pg8 of schematic. 

https://alteraforum.com/forum/attachment.php?attachmentid=14431&stc=1  

3. Why set 0000 at FPP which is default? 

Kindly study and understand, an example of one of the MSEL switch is given: 

Referring MSEL2 set to 0, it is using Flash. Flash(P30) means parallel programming. EEPROM(EPCS or EPCQ) means serial programming. This is the naming system, Flash=parallel, EEPROM=serial. Similarly, info MSEL0 is connected to MAX V can be found and so on. 

4. Look at "rm_cve_fpga_dev_board" pg23, program using EPCQ, original text from that page has given the info, "In order to set the configuration scheme to AS mode, resistor rework needs to be done." Resistor rework=add resistor to the 3.3V that are applied to the MSEL0 till MSEL4 when dip switch is at 1111. 

4a. This means user have to change the original grounded MSEL0 until MSEL4 into powered by 3.3V Vccpgm, but do not connect 3.3V directly and must connect 1kohm resistor to it. Use the breadboard to connect the 1kohm resistor. From basic electronics, that 1kohm is used to lower the current flow and help dispense heat in FPGA. 

4b. This is simplified as it can be, do not skip resistor and direct put 3.3V to MSEL, it will damage the board through high current inrush, in this modifying case, it is not recommended for new learner unless user know how to modify connection. 

 

 

Last edited to grammar, remove all personal pronouns(I, You, We, They, etc), and picture into attachment. 

 

 

Best Regards, 

Tzi Khang, Lim 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

For MSEL is just for telling the FPGA Cyclone V know where will it load the configuration file. My problem right now is programing the ECPQ256. I have attached picture of error  

https://www.alteraforum.com/forum/attachment.php?attachmentid=14437
Altera_Forum
Honored Contributor I
317 Views

 

--- Quote Start ---  

Hi John, 

 

Please refer to the following manual for the Cyclone V E Dev Kit :  

 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/rm_cve_fpga_dev_bo... 

 

The following is taken from the Cyclone V E kit manual: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=14427  

 

What this means is that, to use EPCQ device , you may have to rework the board with 10K resistors as shown in the figure. Before proceeding , please check your board if this configuration is already present. If so, then you just need to modify the SW settings and try. If not, then you need to get 10K resistors and wire the respective signals as shown in the schematic, change the SW settings and then try. 

 

-Abr 

--- Quote End ---  

 

 

10K resistor is on the board. The problem is I kept failing programing the EPCQ Device by .jic file.
Altera_Forum
Honored Contributor I
317 Views

Hi, 

 

It seems that your board has these already in place. Then I suggest you change the SW switch settings to reflect the AS mode. From the image you posted earlier, I see that the programming mode is in JTAG and not AS (note the JTAG signal chain TDI/ TDO). You need to change this mode to Active Serial in the upper right corner of the Programmer window. This will probably clear out the devices listed . You will have to add the EPCQ device again after changing the Programming mode. After the device is added successfully, select your .jic file and then the Erase, Program and Verify options and proceed. It should work this time.
Altera_Forum
Honored Contributor I
317 Views

Hi,  

I do not program EPCQ directly. I program it via JTAG connection. If I pick the Active Serial Programming, it won't work, I tried it and it doesn't work.
Altera_Forum
Honored Contributor I
317 Views

 

--- Quote Start ---  

Hi,  

I do not program EPCQ directly. I program it via JTAG connection. If I pick the Active Serial Programming, it won't work, I tried it and it doesn't work. 

--- Quote End ---  

 

 

Hi John, 

Well, as per checked thoroughly in datasheet, it never written any way of JTAG to program EPCQ, it writen only EPCQ is programmed through 6 pin AS header. And this means through 6 pin header will be using sof or pof file. Besides, jic file=JTAG indirect programming, and not applicable to load jic while connecting that 6 pin AS header. 

Also, JTAG in datasheet shows only connected to flash P30 family memory and not EPCQ. 

 

So, it is not supported in this dev kit officially. Manual rework of connecting resistor can be done as per follow the datasheet, but nothing exact connection is given. That 10k resistor is built on board for nstatus, nconfig, and config_done so no need to connect it is correct. 

You may try pof file through JTAG port for EPCQ and share the result as I do not have access to that board. 

 

 

Sincerely hope you can get back to reply as soon you see this. Was trying to help you 

Many thanks.
Altera_Forum
Honored Contributor I
317 Views

 

--- Quote Start ---  

Hi John, 

Well, as per checked thoroughly in datasheet, it never written any way of JTAG to program EPCQ, it writen only EPCQ is programmed through 6 pin AS header. And this means through 6 pin header will be using sof or pof file. Besides, jic file=JTAG indirect programming, and not applicable to load jic while connecting that 6 pin AS header. 

Also, JTAG in datasheet shows only connected to flash P30 family memory and not EPCQ. 

 

So, it is not supported in this dev kit officially. Manual rework of connecting resistor can be done as per follow the datasheet, but nothing exact connection is given. That 10k resistor is built on board for nstatus, nconfig, and config_done so no need to connect it is correct. 

You may try pof file through JTAG port for EPCQ and share the result as I do not have access to that board. 

 

 

Sincerely hope you can get back to reply as soon you see this. Was trying to help you 

Many thanks. 

--- Quote End ---  

 

 

.pof file is used for flash, it's not for AS programing. I tried it but it doesn't work out.
Altera_Forum
Honored Contributor I
317 Views

Hi John, 

 

Since the EPCQ device is connected to the MAX V system controller, I think the MAX V doesn't allow user to access the EPCQ device. This is documented for the Cyclone V GT Development kit here https://www.altera.com/support/support-resources/knowledge-base/solutions/rd02112014_88.html  

 

You may need to modify the MAX V image to gain access to the EPCQ device. I suggest you contact Altera support and confirm if you need to do it as mentioned in the link above. If this is not the case, you could also ask them how you can program the EPCQ thats on your V E Kit.
Altera_Forum
Honored Contributor I
317 Views

Hi Guys, 

I don't know if the problem was solved. 

I had the same one and I solved it. 

The MAX V controller doesn't allow to write the EPCQ with the jtag connector. 

First you should set the switches to tell you are using the AS. 

Second you should rework the resistors R16 to R18 and R22 to R23. 

Then you should reprogram the MAX V to inhibit the PFL but only the outputs to the FPGA config inputs. You can use the source code provides with the kit. 

It' is a shame that Altera doesn't explain this in the documentation and hasn't developed a pof to correct the problem. 

Now I cant write a jic to the EPCQ. 

And it works. 

 

I'haven't gone deeper yet but these actions inhibit the embeded blaster II. I think it should be a clock problem, but for my personal use the embeded blaster II is useless. 

I will post a solution if i have enought time. 

Regards every body.
Altera_Forum
Honored Contributor I
317 Views

 

--- Quote Start ---  

Hi Guys, 

I don't know if the problem was solved. 

I had the same one and I solved it. 

The MAX V controller doesn't allow to write the EPCQ with the jtag connector. 

First you should set the switches to tell you are using the AS. 

Second you should rework the resistors R16 to R18 and R22 to R23. 

Then you should reprogram the MAX V to inhibit the PFL but only the outputs to the FPGA config inputs. You can use the source code provides with the kit. 

It' is a shame that Altera doesn't explain this in the documentation and hasn't developed a pof to correct the problem. 

Now I cant write a jic to the EPCQ. 

And it works. 

 

I'haven't gone deeper yet but these actions inhibit the embeded blaster II. I think it should be a clock problem, but for my personal use the embeded blaster II is useless. 

I will post a solution if i have enought time. 

Regards every body. 

--- Quote End ---  

 

 

Yeap, the resistors rework should work as I told earlier if look at the datasheet connection, just that I do not have the board, but it shouldn't be an issue.
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