Cyclone V E Development kit sdram parameters

[töz00]

Hello,

I have a Cyclone V E Development kit. I want to set up Sdram for heavy nios II code.

What is the parameters of sdram controller IP for Cyclone V E?

Is there any sdram example for this kit?

[NurAida_A_Intel]

Hi Sir,

Welcome to Intel Community.

As per my understanding, you are looking for design guideline or example design of the SDRAM controller. Please let me know if I understand this correctly.

If yes, you may refer to this EMIF handbook for the design guideline : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_plan.pdf

Hope this helps.

Thanks

Regards,

Aida

[BoonT_Intel]

Hi Sir, you may install the cyclone V E dev kit installation that can get from this link - https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-e.html

There should be the DDR3 example or board test system design that you can open the IP GUI to check the parameters.

[BoonT_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.