I have a Cyclone V E Development kit. I want to set up Sdram for heavy nios II code.
What is the parameters of sdram controller IP for Cyclone V E?
Is there any sdram example for this kit?
Welcome to Intel Community.
As per my understanding, you are looking for design guideline or example design of the SDRAM controller. Please let me know if I understand this correctly.
If yes, you may refer to this EMIF handbook for the design guideline : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/external-memory/emi_plan.pdf
Hope this helps.
Hi Sir, you may install the cyclone V E dev kit installation that can get from this link - https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-e.html
There should be the DDR3 example or board test system design that you can open the IP GUI to check the parameters.
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