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Cyclone V GT Devel board design examples

Seadog
Beginner
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I am doing a design using the Cyclone V GT development board (https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cy...)

The provided SDK has a 'golden' project and top-level RTL file.  But there are no included IP core examples.  In particular, I would like to have the trace delay and skew data for implementing a memory controller for the on-board DDR3 memory array(s).  I can configure a memory controller, but without those board parameters, reliable operation of the memory is problematic.

Also, there are numerous connections between the FPGA and MAX V and MAX II CPLDs.  I think the MAX II implements a USB Blaster; is it expected that the FPGA provides anything (reference clock, etc.) to the CPLDs, or can those connections be safely ignored?

 

Thanks  

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