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Cyclone V GX C5 CRC_ERROR pin

BillP_
Novice
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I have a vendor (Terasic) board and I turned on the CRC_ERROR pin.  Quartus Prime complained that Pin V20 is mapped twice.  Is there a reference to the what dedicated pin is mapped to CRC_ERROR for the Cyclone V series?  I have the handbook, device overview and data sheet.  However,  I could not locate a reference to tie pad V20 to CRC_ERROR.

 

Our intent is to transition to a custom design and currently this pin is a 3.3V LTTL input, but I can remap that to another pin.  I understand that it should be connected to VCCPGM via a pull-up.  I just wanted to be certain to reserve this pin for eventual dedicated use as the CRC_ERROR pin.

 

Thanks for any references and sorry if I have missed this information somewhere.

 

Sorry, it is an F27 package.  Probably because of the package options, there are a lot of possibilities and maybe a manual has not been published with the dedicated pins for this reason.  I was looking for the banks to pad mapping as well, but the pin planning tool seems to provide this.  I will take a look at the layout guide again.

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NurAiman_M_Intel
Employee
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Hi,


Thanks for the update. Just to let you know, this case was set to close as we did not received any update from you after my final response.


For pin assignment for CRC_ERROR and V20, you may refer to pinout file and mapped it accordingly. Do not need to assign using pin planner. Please ensure follow the pinout file and guidelines.


https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html#cyclone%C2%AEvdevices


Regards,

Aiman


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NurAiman_M_Intel
Employee
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Hi,


Per the device connection guidelines below,


"When you use the dedicated CRC_ERROR pin configured as an open-drain output, connect this pin through an external 10-kΩ pull-up resistor to VCCPGM. When you do not use the dedicated CRC_ERROR pin configured as an open-drain output and when this pin is not used as an I/O pin, connect this pin as defined in the Quartus Prime software. The I/O buffer type is reported in the fitter report."


https://www.intel.la/content/www/xl/es/content-details/714106/cyclone-v-gx-gt-e-sx-st-and-se-device-family-pin-connection-guidelines.html


I don't understand what this has to do with Pin V20?


Regards,

Aiman



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NurAiman_M_Intel
Employee
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Hi,


Any update for this case?


Regards,

Aiman


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NurAiman_M_Intel
Employee
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We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


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NurAiman_M_Intel
Employee
766 Views

Hi,


Thanks for the update. Just to let you know, this case was set to close as we did not received any update from you after my final response.


For pin assignment for CRC_ERROR and V20, you may refer to pinout file and mapped it accordingly. Do not need to assign using pin planner. Please ensure follow the pinout file and guidelines.


https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html#cyclone%C2%AEvdevices


Regards,

Aiman


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