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Cyclone V GX, Custom PHY, using fPLL as TX PLL

SimonRichter
New Contributor I
366 Views

Hi,

I'm trying to get six independent SATA links on a Cyclone V GX with six transceivers, as far as I can see this should be possible.

My approach for clocking would be to run all the channel PLLs in CDR mode for RX clocking, and generate the TX serial clock using the fPLL, which can feed it to the x6 clock network. The TX parallel clock is then generated in the channel clock divider, as the fPLL does not drive the parallel clock.

  1. Can I specify that with the Custom PHY megafunction, or do I need to go a different path here? Simply configuring a Custom PHY in duplex mode instantiates one CDR and one CMU PLL per channel, and these fail to merge afterwards.
  2. Can I use a single fPLL for all channels, or should I use both (one for channel 0-2, one for channel 3-5)?
  3. If I want to support both 1.5Gbps and 3Gbps, can I divide the serial clock in the channel, or do I need to set up a separate fPLL and set up clock distribution accordingly?
  4. Can I run the fPLL off the system clock for the rest of the fabric (generated in a normal PLL), or should I add a separate reference clock to my board?

Simon

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1 Solution
SimonRichter
New Contributor I
264 Views

Okay, I have a valid PLL configuration now: two fPLLs that feed as external PLLs into three transceivers each.

For reference: the fPLL's output port is not valid as an input clock for a transceiver block if reconfiguration is enabled, because that routes the clock through the per-output C divider to allow reconfiguration to set up a divisor here, this gives an error message that the CLKCDRLOC port on the transceiver is not properly connected. The knowledge base entry for this is incomplete: connecting to outclk_0 only works if PLL reconfiguration is disabled.

The solution here is to disable reconfiguration for the fPLLs, or enable access to the DPA outputs in the PLL configuration and connect the clock to phout[0], then the design compiles.

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7 Replies
Deshi_Intel
Moderator
342 Views

HI Simon,


Pls see my comment below.


I'm trying to get six independent SATA links on a Cyclone V GX with six

transceivers, as far as I can see this should be possible.

  • I am sorry to say but likely it's impossible to fit 6 duplex channel into 6 transceiver channel as CMU PLL itself will consume one of the RX channel
  • You are going to need bigger FPGA device with more transceiver channel
  • Rx channel can only be used either as Rx channel CDR or as CMU PLL


- Can I specify that with the Custom PHY megafunction, or do I need to

go a different path here? Simply configuring a Custom PHY in duplex mode

instantiates one CDR and one CMU PLL per channel, and these fail to

merge afterwards.

  • CustomPHY IP required to use CMU PLL instead of fPLL for clocking Tx channel. So, you can't use fPLL. You need to use CMU PLL instead


- Can I use a single fPLL for all channels, or should I use both (one

for channel 0-2, one for channel 3-5)?

  • You need to use CMU PLL since you are using CustomPHY IP


- If I want to support both 1.5Gbps and 3Gbps, can I divide the serial

clock in the channel, or do I need to set up a separate fPLL and set up

clock distribution accordingly?

  • You need to use 2 PLL


- Can I run the fPLL off the system clock for the rest of the fabric

(generated in a normal PLL), or should I add a separate reference clock

to my board?

  • Sorry, I don't quite understand your question here. Can you elaborate further ?


Thanks.


Regards,

dlim



SimonRichter
New Contributor I
339 Views

Hi,

okay, I'm still trying to wrap my head around this.

Table 2-4 in CV-53002 mentions an x1_fPLL line that goes to three channels each (so I'd have to run both fPLLs with identical settings), and table 2-6 mentions a path for bonded configurations

    fPLL » x1_fPLL » central clock divider » x6 » individual clock divider » serializer

Both of these sound like I can feed the x1_fPLL line directly into the channel divider, which would free the channel PLL for CDR. Since I don't need bonding mode, I can skip the step where the divider output is then fed back into the x6 network. Each group of three is then limited by the slowest device, but that is probably not a problem in practice.

I can see that this isn't possible with the Custom PHY, would it help to switch to Native PHY?

Regarding the clock source for the fPLL, table 2-1 answers my question -- the routing I had in mind would be very jittery, so I'll feed in a high-speed clock via GXB_REFCLK.

   Simon

SimonRichter
New Contributor I
265 Views

Okay, I have a valid PLL configuration now: two fPLLs that feed as external PLLs into three transceivers each.

For reference: the fPLL's output port is not valid as an input clock for a transceiver block if reconfiguration is enabled, because that routes the clock through the per-output C divider to allow reconfiguration to set up a divisor here, this gives an error message that the CLKCDRLOC port on the transceiver is not properly connected. The knowledge base entry for this is incomplete: connecting to outclk_0 only works if PLL reconfiguration is disabled.

The solution here is to disable reconfiguration for the fPLLs, or enable access to the DPA outputs in the PLL configuration and connect the clock to phout[0], then the design compiles.

Deshi_Intel
Moderator
303 Views

HI,


Your understanding of fPLL clocking capability is correct in the sense that we should be able to use fPLL to clock multiple transceiver channel using xN clock network.


Custom PHY is tied up with limitation of using CMU PLL only


For NativePHY, we have option to enable "use external Tx PLL"

  • With this setting enable, it will expose one clocking port that we can connect to external fPLL IP


Feel free to test it out.


Thanks.


Regards,

dlim


SimonRichter
New Contributor I
291 Views

Hi,

that sounds like what I need.

I've investigated a bit, and if I read the SystemVerilog code right, it will unconditionally create a TX PLL per channel even in "external PLL" mode (the respective section is instantiated every time the TX path is enabled).

Is this generated PLL supposed to be merged with an existing fPLL instance, or is it supposed to be removed as the clock selection mux instantiated behind it removes its fanout?

The clock ports seem to be named, and .clkffpll is mentioned twice in altera/altera_xcvr_generic/cv/cv_tx_pma_ch.sv:

altera/altera_xcvr_generic/cv/cv_tx_pma_ch.sv:233://  .clkffpll       (wire_clk[3]      ),
altera/altera_xcvr_generic/cv/cv_tx_pma_ch.sv:268:    .clkffpll       (1'b0/*TODO*/     ),

One of these is a comment, and the other one is a hardcoded zero in a "synopsys translate_off" block, so it seems I cannot connect anything to this port, which would explain why I get an error message if I instantiate the Native Transceiver PHY with a PLL count of 4 and select PLL 3 as the main PLL (which would translate to

pll_sel = 3

and therefore to

tx_cgb.x1_clock_source_sel = "ffpll"

I'll investigate further, but it seems to me that I need to skip the MegaWizard here, and instantiate the components directly, is that correct?

   Simon

Deshi_Intel
Moderator
277 Views

HI Simon,


There are a lot of background processing happened in Quartus compilation flow.


Typically physical design block (like PLL) merging process will only happen in fitter compilation stage.


You can check your fitter report to see how many PLL is used and find out more detail in PLL usage summary report to be sure


Thanks.


Regards,

dlim


Deshi_Intel
Moderator
238 Views

Thanks for the sharing !


This will definitely benefit the forum community.


Alright, hopefully you are able to proceed with your project development now. I am now setting this case to closure.


Regards,

dlim


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