after I've found a valid clock routing for using all transceiver channels in full-duplex mode with CDR on the receive path and the transmit path clocked by the fPLLs, two small questions remain:
The goal would be to select between 3Gbps and 1.5Gbps on a per-port basis.
As I understand it, you have some inquiries related to the TX local clock division factor. For your information, this clock division is located inside the TX PMA. It allows you to use a single TX PLL frequency to achieve two different data rate which is a division by 2. For example, if you want to implement 3G and 1.5G. You can configure the fPLL to output 1.5GHz frequency (for 3Gbps). Then, when you would like to operate at 1.5Gbps, you can reconfigure the channel to have division of 2. With this, you do not need to reconfigure the fpll.
Please let me know if there is any concern. Thank you.
As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.