I am looking to implement DP to MIPI DSI using the Cyclone V GX. I will need to synthesize the MIPI pixel clock from the DP stream using the fPLL. As I have 2 DSI channels I will aslo need 2 PLL's (1/channel). Can the cyclone V GX handle this? Can I use a fPLL and 2 PLL's at the same time?
Thanks for your inquiry.
The Cyclone V device family contains fractional PLLs that can function as fractional PLLs or integer PLLs.
The output counters in Cyclone V devices are dedicated to each fractional PLL that support integer or
fractional frequency synthesis.
We can refer to Table 4 of doc below:
Depends on which member code you are using, there are multiple number of fPLLs can be used.
You can refer to doc below for more Cyclone V PLL information: