Cyclone V GX: PLL on LVDS banks & fPLL

[PascalPolygon]

Hello guys,

I am looking to implement DP to MIPI DSI using the Cyclone V GX. I will need to synthesize the MIPI pixel clock from the DP stream using the fPLL. As I have 2 DSI channels I will aslo need 2 PLL's (1/channel). Can the cyclone V GX handle this? Can I use a fPLL and 2 PLL's at the same time?

Regards,

Pascal. 

[EngWei_O_Intel]

Hi Pascal

Thanks for your inquiry.

The Cyclone V device family contains fractional PLLs that can function as fractional PLLs or integer PLLs.
The output counters in Cyclone V devices are dedicated to each fractional PLL that support integer or
fractional frequency synthesis.

We can refer to Table 4 of doc below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51001.pdf

Depends on which member code you are using, there are multiple number of fPLLs can be used.

You can refer to doc below for more Cyclone V PLL information:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

Thanks.

Eng Wei

[PascalPolygon]

@EngWei_O_Intel 

Thank you for the reply. Is it possible to use a mixture of fPLL and integer PLL in the same design?

Regards,

Pascal.

[EngWei_O_Intel · Accepted solution]

Hi Pascal

Yes you can.

Thanks.

Eng Wei

[EngWei_O_Intel]

Hi Pascal

We do not receive any response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei

[PascalPolygon]

Hello @EngWei_O_Intel 

I think you answered my question. Thank you.