This is my first post on the Intel FPGA community! I believe this can be done with the Cyclone V GX transceiver, but can someone please confirm:
- Receive one LVDS data channel with a separate LVDS clock signal, data rate of 1.04 Gbps, serialization factor of 16 (clock rate of 65 MHz).
- Assuming this is possible, is there an example design such an application? This transceiver is surprisingly complex.
I've spent most of the day learning about the Cyclone V GX transceiver and searching for examples and answers to my specific question but found nothing useful. Any help is appreciated!
As I understand it, you would like to configure the CV transceiver to run at 1.04Gbps with SERDES factor of 16. For your information, you can use the Native PHY IP to configure the CV transceiver. As I checked using the Native PHY IP, there should be no issue to achieve your target configuration.
For your information, there seems to be no specific example design per your target configuration. I have sent you a simulation example previous from wiki to your email for reference. This example is showing a CV Native PHY running with bitslip mode. You refer to the example on the modules required and interconnection between them. Hopefully it helps a quicker start.
I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.