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MKlee2
New Contributor I
738 Views

Cyclone V Gbx Transceivers - can't fit more than 4, should be able to use 6? Error (14566): The Fitter cannot place 5 periphery component(s) due to conflicts with existing constraints (5 Channel PLL(s)).

Device: 5CSXFC6C6U23C7

 

Problem:

I'm trying to use a transceiver with 5 channels (2.5Gbps preset with more channels), but the fitter throws me an error about occupied pll locations.

From my understanding, I should be able to use up to 6 plls, so 5 should be fine?

If I reduce the channels to 4 it works without an error.

I thought it might try to double the plls for tx/rx or somthing, but in this case the 4 channel configuration should also fail?

I also tried to use a different bonding mode to no avail, ending up in a different error (see atteched log).

 

Additional info (used components):

1x Transceiver conf. to use 2.5Gbps preset (input clock changed to 100MHz Datarate changed to 2000Mbps) (Cyclone V native PHY)

1x reset controllerconf. 5 TX-PLLs, 5 Channel, 100MHz rest @ default

1x reconfig controller 10 interfaces (to match port size of xcvr)

 

Logs:

1x Described error

1x With bonding xN + corrosponding reconfig and reset controller

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6 Replies
CheePin_C_Intel
Employee
135 Views

Hi Matthias, As I understand it, you observe some Fitter error during your compilation with CV XCVR design. As I check the CV part that you are using, there are total of 6 XCVR channels. By default, you should be able to implement maximum of 5 duplex XCVR with one channel reserved for CMU PLL. Would you mind to share a simple test design with Native PHY which could replicate the error observation so that I could further look into it? Thank you.
MKlee2
New Contributor I
135 Views

Thank you for your answer, attached is a simple test design.

I believe it might be related to my pin planning/placing, maybe you point out what went wrong.

MKlee2
New Contributor I
135 Views

I played a bit around with my pin planning and it seems to work if I leave AB2/1 and Y2/1 free and use F2/1 D2/1 instead.

Could you please tell me why I need to leave out this specific(?) pins? I also tried leaving out other pins on the same bank and use AB2... again,

but this would result in an error again.

CheePin_C_Intel
Employee
135 Views

​Hi sorry for the delay, thanks for attaching the design. I am currently running compilation with the design. I will update you on the finding by end of the week. Please ping me if I do not get back to you.

CheePin_C_Intel
Employee
135 Views

​Hi,

 

As I look into your design, I can replicate the Fitter error when compiling your design. I notice that you have placed channels to physical channel of CH 1 and CH4 in the design. For your information, the CMU PLL is only available in physical CH1 and CH4. Therefore, you would need to leave either one of these two CHs unused for CMU PLL purpose. This also explain why when you leave AB2/1 and Y2/1 unused, the design can pass Fitter compilation. Note that if you leave K2/1 and H2/1 unused, your design will also pass compilation since there is one CMU PLL here as well.

 

Please let me know if there is any concern. Thank you.

MKlee2
New Contributor I
135 Views

Thanks for the reply this is the information I was missing!

Reply