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Cyclone V LVDS simulation errors

sousbois
Beginner
814 Views

Hello,

 

I'm running into simulation errors with a simple project instantiating a ALTLVDS_TX block on a cyclone V FPGA. Everything (admittedly not much) runs fine if I comment the block out... I also tried re-generating the IP with different ports / options, but didn't have any luck.

This is with Quartus 22.1 and questa 21.2.

I get the following error:

# vsim work.lvds_tb

# Start time: 09:49:13 on Jan 30,2023

# ** Note: (vsim-3812) Design is being optimized...

# ** Error: $MODEL_TECH/../intel/vhdl/src/cyclonev/mentor/cyclonev_atoms_ncrypt.v(38): in protected region

# Optimization failed

# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=1, Warnings=0.

# Error loading design

# End time: 09:49:15 on Jan 30,2023, Elapsed time: 0:00:02

# Errors: 1, Warnings: 0

 

Thanks for any help !

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1 Solution
RichardTanSY_Intel
759 Views

Since you are using Quartus Standard 22.1 version, I suggest to use Nativelink so that it will automatically compile your design, Intel IP, simulation model libraries, and testbench.
You may checkout the document and video here:

https://www.intel.com/content/www/us/en/docs/programmable/683080/22-1/using-nativelink-simulation.html

https://www.youtube.com/watch?v=PmVVXQchv2c

 

The .qar project can be generated by going to Project > Achieve Project.

 

Best Regards,

Richard Tan

 

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

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5 Replies
RichardTanSY_Intel
802 Views

May I know which simulation flow are you using? Nativelink or scripted simulation flow?

Could you provide the design .qar file so I could check it from my side? (you can generate the .qar file by achieving the project)

And please provide the steps you used to simulate the design and produce the error.


Best Regards,

Richard Tan


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sousbois
Beginner
798 Views

Hi Richard,

Thank you for your quick response. I wasn't able to find a .qar file in my project, but I uploaded my output directory.

I am not using Nativelink. I just started a questa work library and compiled my test bench along with the generated vho file from Quartus (attached).

I get the above error when I attempt to launch the test bench in Questa.

Best regards,

Sam Underwood

 

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RichardTanSY_Intel
760 Views

Since you are using Quartus Standard 22.1 version, I suggest to use Nativelink so that it will automatically compile your design, Intel IP, simulation model libraries, and testbench.
You may checkout the document and video here:

https://www.intel.com/content/www/us/en/docs/programmable/683080/22-1/using-nativelink-simulation.html

https://www.youtube.com/watch?v=PmVVXQchv2c

 

The .qar project can be generated by going to Project > Achieve Project.

 

Best Regards,

Richard Tan

 

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

sousbois
Beginner
751 Views

Worked like a charm, thanks !

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RichardTanSY_Intel
732 Views

Thank you for acknowledge the solution provided. 

I’m glad that your question has been addressed, I now transition this thread to community support. 


Best Regards,

Richard Tan


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