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Hello,
I'm trying to figure out how large a design I can implement in a Cyclone V FPGA. It's widely documented that the device can accommodate 110K LEs. But what's an LE? An inverter? A basic gate? A F/F? A 256 bit shift reg?
TIA for any guidance on this. A spec of some kind on the subject would be really helpful.
Again, thanks,
Bill McDonald
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Hello Bill,
I assume the article FPGAs: System gates or logic cells/elements? can be helpful: www.eetimes.com/fpgas-system-gates-or-logic-cells-elements
A fragment from the mentioned article:
"Each LUT could be used to represent a function that would be the equivalent to some number of equivalent gates. For example, someone once told me that a 4-input LUT could be used to represent functions that were the equivalent of anywhere between 1 and 20+ regular logic gates."
I would recommend to try to implement your project in the Quartus design system for Intel/Altera Cyclone V family. This device family is supported via free Intel Quartus Prime Lite Edition. (https://fpgasoftware.intel.com/?edition=lite).
Regards,
Martin
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Hi Martin,
Sounds like exactly what I'm looking for; I'll definately check it out.
Many thanks,
Bill
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Hi Bill
You can refer to definition here:
Thanks.
Eng Wei
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Hi Eng Wei,
Many thanks. This is very helpful and nicely supplements the information previously sent by Martin.
Best,
Bill
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Hi Bill
Hope your issue is resolved. I am transitioning this thread for community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei
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