Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20693 Discussions

Cyclone V SX transceiver Bonding

Smith222122
Beginner
458 Views

Hello there,

 

My question is:

 

Do transceiver channels need to be within the same transceiver bank in order to use them in bonded mode?

In my Cyclone V SX device, I have two transceiver banks with 3 transceiver channels each. Is the max amount of transceiver channels I can bond at once 3?

 

Thank you for any help!

0 Kudos
3 Replies
Kshitij_Intel
Employee
406 Views

Hi,


It not mandatory, you can place channels in other transceiver bank also but that it consumes more PLL resources. Each transceiver bank consumes one PLL and one master CGB. So, it's better if you place the channel in same transceiver bank.


Thank you

Kshitij Goel


0 Kudos
Kshitij_Intel
Employee
402 Views

Hi,


In a bonded configuration, bonded channels must be placed contiguously without leaving a gap between the channels, except when the gap channel is a CMU PLL used for the bonded channels. The contiguous channels may span across many banks for bonded mode. For example, in x8 bonding, the bonded channels may span across 3 to 4 banks with the condition that there must be no gap between the channels except when the gap is due to the channel used for CMU PLL.


https://www.intel.com/content/www/us/en/docs/programmable/683586/current/transmitter-clock-network.html



Thank you

Kshitij Goel



0 Kudos
Kshitij_Intel
Employee
387 Views

Hi,


As We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


Thank you

Kshitij Goel


0 Kudos
Reply