Cyclone V: Set LVDS output buffer delay

[Altera_Forum]

Hello everyone, 

 I have an application where I'd like to compensate board trace length differences using (fixed) output delays. The outputs are driven by the dedicated SERDES hardware with an LVDS I/O standard. I have set the assignments like this:  set_instance_assignment -name OUTPUT_BUFFER_DELAY 119 -to IO_B4A_B52_AG14_P   IO_B4A_B52_AG14_P is the name of the positive LVDS output pin. This looks fine, but the fitter complains:  Error (169226): I/O standard LVDS on pin IO_B4A_B52_AG14_P cannot have Output Buffer Delay logic option setting 119  Is it impossible to set output delays for LVDS buffers? Or do I need to assign them in some different way?  Thank you! Best regards, Philipp

[Altera_Forum]

Your assignment is correct. However, LVDS is not a supported I/O standard when using the programmable output delay. 

 Refer to the 'programmable ioe features in cyclone v devices' section and table 5-24 in the 'cyclone v device handbook (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf)'.  Cheers, Alex

[Altera_Forum]

Hi Alex, 

 thanks for your reply! Will need to look for another way of improving my signal integrity then...  Best regards, Philipp