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Honored Contributor I
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Cyclone V SoC DK: how to configure awprot/arprot of EMAC?

We're trying to get ethernet working in the Normal/Non-Secure World on the Cyclone V SoC DK board, but are running into a roadblock right now, where we cannot find a way to configure the security status of the memory accesses done by the EMACs. 

 

The USB and SDMMC controllers have a hprotpriv_i bit in the l3master register to control the value for arprot/awprot during memory access. The description of the EMAC in the "Functional Description" section (p. 5-5 of cyclone v hard processor system technical reference manual 2016.10.28 (https://www.altera.com/documentation/sfo1410143707420.html)) also mentions setting arprot/awprot through its l3master register: 

--- Quote Start ---  

You can use the system manager's l3master register to control the EMAC's ARCACHE and AWCACHE signals, 

by setting or clearing the ( arcache, awcache ) and ( arprot, awprot ) bits. These bits define the cache 

attributes for the master transactions of the DMA engine in the EMAC controllers. 

--- Quote End ---  

 

 

However, the actual description of the l3master register for EMAC (p. 5-46) only defines the a[rw]cache_i fields to control caching and buffering. So is there some way to control a[rw]prot_i for memory accesses of the EMAC controllers?
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