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Altera_Forum
Honored Contributor I
1,278 Views

Cyclone V bidirectional half-duplex LVDS?

Dear All, 

 

We are designing a board with a Cyclone V connected to another (already existing) board via a bidirectional half-duplex LVDS link. We would prefer to use only 2 pins of the FPGA to implement both the Rx and the Tx. I tried the following: 

  • I defined an ALTIOBUF "As bidirectional buffer", and "Use differential mode". See attached file.  

  • I used the IO_STANDARD "DIFFERENTIAL 2.5-V SSTL CLASS I".  

  • I instanciate the ALTIOBUF in the natural way:  

 

Ulvds : altiobuf_lvds port map  

(  

datain => Tx_data, 

dataio => FPGA_PIN_P, 

dataio_b => FPGA_PIN_N, 

dataout => Rx_data, 

oe => output_enable, 

oe_b => output_enable 

); 

 

(By the way, the oe_b is the output enable for the complemented signal, or the complement of the output enable?) 

 

It seems that Quartus can compile the design, and the Pin-Out File in the report contains 

FPGA_PIN_P : U27 : bidir : Differential 2.5-V SSTL Class I : : 5B : N  

FPGA_PIN_N : U28 : bidir : Differential 2.5-V SSTL Class I : : 5B : N  

 

Is it correct? It seems contradictory to the documentation and other posts related to this question (or related to BLVDS). 

 

To be complete: Cyclone V: 5CEBA9F31C8, Quartus Prime 16.1.0 Build 196 10/24/2016 SJ Lite Edition. 

 

Thank you
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6 Replies
Altera_Forum
Honored Contributor I
137 Views

Yes, this is correct. Another area where Cyclone V differs from previous families. This would not work with Cyclone IV. DIFFERENTIAL 2.5-V SSTL CLASS I cannot be tri-stated there. However, Cyclone IV supports Bus LVDS. Cyclone V doesn't. 

 

You seem to get "oe_b" for free - even if you don't want it. Tie it off low if you're happy using a single ended signal driving "oe". 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
137 Views

Thank you a_x_h_75! 

 

We are happy that it is correct. However, I am not sure to understand the AN522 "Implementing Bus LVDS Interface in Supported Altera 

Device Families", on page 6, there is a footnote "DIFFIO_TX pin does not support true LVDS differential receivers". Does it mean that for our purpose one should *not* use DIFFIO_TX pins, but DIFFIO_RX pins work well (can be transmit/receive/be tri-stated). Indeed Quartus selected some DIFFIO_RX pins. Nevertheless it seems that our goal is somehow similar to Bus-LVDS?
Altera_Forum
Honored Contributor I
137 Views

You *cannot* use the DIFFIO_TX pins on Cyclone V for differential input signals. These signals connect to the dedicated TX channels. The DIFFIO_RX pins can be used, for output signals, by virtue of their emulated DIFFOUT capability. So, for a bidirectional differential signal you must use a DIFFIO_RX pair. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
137 Views

Does "emulated DIFFOUT capability" means that we need an "External resistor network"?  

See "Cyclone® V Device Family Pin Connection Guidelines - PCG-01014-2.5" 

Is it a good idea to put the external resistor network (for output) and use also the differential input? 

 

Thank you
Altera_Forum
Honored Contributor I
137 Views

I understand that the Cyclone V BLVDS implementation with differential SSTL IO-standard uses the same termination resistors as the AN522 Cyclone III/IV implementation, 50 ohm near series termination and far differential 100 ohm termination at both bus ends. Optionally bias resistors.

Altera_Forum
Honored Contributor I
137 Views

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