Cyclone V speed is much slower

[Altera_Forum]

Hello. I am new to Cyclone V. I took my design for Cyclone III and recompiled it with Quartus II web 13.1. From the timing analyzer, I can see that the maximum clock rate is only 84 Mhz while I was getting 131 Mhz with cyclone III at the same C8N speed grade. The timing recommendation is incomprehensible. Would anyone who knows cyclone V well tell me if this is expected? Is Cyclone V significantly slower than Cyclone III? This doesn't make sense. 

 Thanks a lot.  Jixiang

[Altera_Forum]

Move to a later version of Quartus (15.0) 

The timing models were not final in Quartus 13.1 for Cyclone V and were very conservative (overly so).  You should see much improved timing performance in Quartus 15.0.  Pete

[Altera_Forum]

Thanks Pete. I have done just that. The speed does improved to 88 Mhz. However, it's still significantly slower than Cyclone III or Cyclone IV which I get comparable performance.https://www.alteraforum.com/forum/attachment.php?attachmentid=10792

[Altera_Forum]

Ok that sounds wrong. I expect a significant increase in performance for Cyclone V from Cyclone III. My guess is there are some false paths that are getting ignored in the conversion, (IE the PLL Changed, so the old SDF file isn't valid anymore). 

 I would look at that. If you can send a timing report for both the designs we can look at it.  Pete

[Altera_Forum]

Cyclone V is of much newer technology as compare to the Cyclone III. Thus, we should expect generation V to have much better performance than Cyclone III. As mentioned by anakha, I believe we might need to further look into the timing constraints to see if there is any anomaly.

[Altera_Forum]

That's a good news because I do plan to move all to Cyclone V and the performance is important.  

 I do not seem to find a way to generate a timing report file. I opened the timeQuest analyzer and I see that I can write a SDC file but that isn't a timing report, is it?   Thanks in advance.  Jixiang

[Altera_Forum]

I did find a report file .sta.rpt. Is this what I should send you for both devices? Would you give me an email address? 

 Thanks in advance  Jixiang

[Altera_Forum]

It does sound like some timing specs are missed. Have some paths for different names? 88 MHz is very slow and points to poor quality design.

[Altera_Forum]

You are perhaps right but this is a new issue just to Cyclone V. I have done just fine with Cyclone 1-4.

[Altera_Forum]

You have to replace pll ip, delete and recreate it then see if there are pll related warnings

[Altera_Forum]

I have just done that. It make no difference. The max freq is still 88mhz.

[Altera_Forum]

Check warnings for any timing constraints that are being ignored because of empty lists.

[Altera_Forum]

Here is the summary from the timing report 

 +-------------------------------------------------------------------------+ ; TimeQuest Timing Analyzer Summary ; +--------------------+----------------------------------------------------+ ; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; F ; ; Device Family ; Cyclone III ; ; Device Name ; EP3C40Q240C8 ; ; Timing Models ; Final ; ; Delay Model ; Combined ; ; Rise/Fall Delays ; Enabled ; +--------------------+----------------------------------------------------+  The max speed is 127.98 Mhz  +-----------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +------------+-----------------+---------------------------------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+---------------------------------------------------+------+ ; 127.98 MHz ; 127.98 MHz ; myclk|altpll_component|auto_generated|pll1|clk[0] ; ; ; 167.22 MHz ; 167.22 MHz ; PLL1IN ; ; +------------+-----------------+---------------------------------------------------+------+  With the exact same design recompiled for Cyclone V  ; TimeQuest Timing Analyzer Summary ; +--------------------+----------------------------------------------------+ ; Quartus II Version ; Version 13.1.0 Build 162 10/23/2013 SJ Web Edition ; ; Revision Name ; F ; ; Device Family ; Cyclone V ; ; Device Name ; 5CEBA4F23C8 ; ; Timing Models ; Final ; ; Delay Model ; Combined ; ; Rise/Fall Delays ; Enabled ; +--------------------+----------------------------------------------------+  The speed is 84.47 Mhz using Quartus ii 13.1 +---------------------------------------------------------------------------------------------------------------+ ; Slow 1100mV 85C Model Fmax Summary ; +------------+-----------------+-------------------------------------------------------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+-------------------------------------------------------------------------+------+ ; 84.47 MHz ; 84.47 MHz ; myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk ; ; ; 218.72 MHz ; 218.72 MHz ; PLL1IN ; ; +------------+-----------------+-------------------------------------------------------------------------+------+

[Altera_Forum]

Thanks. I have checked all warnings. Here is the messages. Sorry, it's long 

 Critical Warning (138069): Setting INCREMENTAL_COMPILATION to "OFF" is no longer supported. Assignment is ignored. To disable partitions, set the IGNORE_PARTITIONS global assignment to "ON" instead. Warning (20013): Ignored assignments for entity "Flex01" -- entity does not exist in design  Warning (20014): Assignment for entity set_instance_assignment -name CLOCK_SETTINGS Clock -to clock -entity Flex01 was ignored  Warning (20014): Assignment for entity set_instance_assignment -name CLOCK_SETTINGS clockx2 -to clockx2 -entity Flex01 was ignored Warning (20028): Parallel compilation is not licensed and has been disabled Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (332164): Evaluating HDL-embedded SDC commands  Info (332165): Entity dcfifo_gkl1  Info (332166): set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_d09:dffpipe16|dffe17a*   Info (332166): set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_c09:dffpipe12|dffe13a*  Critical Warning (332012): Synopsys Design Constraints File file not found: 'Flex01.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks" Info (332110): Deriving PLL clocks  Info (332110): create_clock -period 20.833 -waveform {0.000 10.416} -name PLL1IN PLL1IN  Info (332110): create_generated_clock -source {myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin} -divide_by 8 -multiply_by 125 -duty_cycle 50.00 -name {myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}  Info (332110): create_generated_clock -source {myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 6 -duty_cycle 50.00 -name {myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.  Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk  Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk  Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT from: clkin[0] to: clkout Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty" Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1100mV 85C Model Critical Warning (332148): Timing requirements not met  Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -3.839  Info (332119): Slack End Point TNS Clock   Info (332119): ========= =================== =====================  Info (332119): -3.839 -1940.855 myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk   Info (332119): -0.629 -0.629 PLL1IN  Info (332146): Worst-case hold slack is -1.915  Info (332119): Slack End Point TNS Clock   Info (332119): ========= =================== =====================  Info (332119): -1.915 -1.915 PLL1IN   Info (332119): 0.247 0.000 myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk  Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 0.666  Info (332119): Slack End Point TNS Clock   Info (332119): ========= =================== =====================  Info (332119): 0.666 0.000 myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]   Info (332119): 2.381 0.000 myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk   Info (332119): 9.090 0.000 PLL1IN  Info: Analyzing Slow 1100mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.  Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk  Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk  Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT from: clkin[0] to: clkout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Critical Warning (332148): Timing requirements not met  Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. Info (332146): Worst-case setup slack is -4.424  Info (332119): Slack End Point TNS Clock   Info (332119): ========= =================== =====================  Info (332119): -4.424 -2522.605 myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk   Info (332119): -0.532 -0.532 PLL1IN  Info (332146): Worst-case hold slack is -1.981  Info (332119): Slack End Point TNS Clock   Info (332119): ========= =================== =====================  Info (332119): -1.981 -1.981 PLL1IN   Info (332119): 0.159 0.000 myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk  Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 0.666  Info (332119): Slack End Point TNS Clock   Info (332119): ========= =================== =====================  Info (332119): 0.666 0.000 myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]   Info (332119): 2.323 0.000 myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk   Info (332119): 8.993 0.000 PLL1IN  Info: Analyzing Fast 1100mV 85C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network.  Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL from: refclkin to: fbclk  Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER from: vco0ph[0] to: divclk  Info (332098): Cell: myclk|mypll_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT from: clkin[0] to: clkout Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. Info (332146): Worst-case setup slack is 0.000  Info (332119): Slack End Point TNS Clock   Info (332119): ========= =================== =====================  Info (332119): 0.000 0.000 PLL1IN   Info (332119): 2.113 0.000

[Altera_Forum]

The warning says there is no sdc file and so the compiler (Timequest) goes default and funny.

[Altera_Forum]

The next question is why Altera allows compilation when there is no sdc file. If timing is not entered then such compilation is useless and should have been stpped with something like "very fatal and deadly error"

[Altera_Forum]

Try using the current 15.0 version.

[Altera_Forum]

No sdc file would be a culprit. There's also other assignments for an entity that doesn't exist.

[Altera_Forum]

Thanks to everyone who responded to my problems. I am trying everything to get this resolved. I am using Q 15.0, the latest. I have cleaned up my design but it didn't help. I added pipeline stages in my design but it didn't help. 

 In the timing report, the recommendation is the following  Move 0 combinational nodes before the source and 3 after the destination for the path from corr|...3]~_Duplicate_54 to corr|..._1~mac_pl[0][16] [hide details] Issue: Unbalanced Combinational Logic From: shift_b[1][3]~_Duplicate_54 To: lpm_add_sub:adder_pipe[18]|add_sub_7ic:auto_generated|op_1~mac_pl[0][16] TimeQuest analysis: report timing Nodes to move after dest: 3 Nodes to move before source: 0  This message doesn't make sense to me. Can anyone help me to decipher this?  Thanks in advance.

[Altera_Forum]

Could you post your project?

[Altera_Forum]

from my understanding, newer device doesnt mean it is faster. You will have to look at the speed grade. Even if you choose a newer device but the slowest speed grade, it might still lose to an older device with the fastest speed grade.