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Cyclone VE DDR3 SDRAM controller generation issue

slmel
Novice
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Hi, 

 

I am trying to generate DDR3 SDRAM controller for Cyclone VE FPGA. But there are errors while generation. Please see screen shot below. The Quartus version we are using is 20.1.

 

slmel_0-1621315904734.png

The part we are using is 5CEBA2F23C8N. Could you please help on this issue?

 

Rgds,

Sree

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