Cyclone10 do not support AS config scheme when Configurationn Voltage Standard=2.5V ?

[xytech]

Hi there,

we are using 10CL055YU484C8G, ALL 8 bank VCCIO=2.5V, VCCA=2.5V, VCC_core=1.2V

We planned to use AS config scheme with standard POR delay, however, From latest Cyclone10 LP handbook, section 6.3.1 Table44(as below), there is no corresponding MSEL code for 2.5V Configuration Voltage Standard. Only 3.3V and 3.0V are listed.

1.Does this mean C10 LP devide does not support AS config scheme when VCCIO=2.5V? That sounds very weird......and we do notice that in previous version of cyclone handbook that 2.5V is listed here. Please help confim. Thanks.

2.If we need to use 4M-Bytes third party flash IC for AS, is it feasible to choose a flash IC whose VCC=3.3V? As C10's VCCIO=2.5V, it concerns that 3.3V logic may damage FPGA, or at least they may not recognizable (voltage-level-incompatible) with each other . Maybe should I insert a 2.5V-to-3.3V voltage level transfer interfaceing IC between C10 FPGA and Flash? Also, hope you could recommend some third party part numbers. Thanks.

[xytech]

up

[xytech]

Hi, any Intel expert could ​support on this? Thanks!

[xytech]

Could anyone help on this? Thanks!​

[xytech]

....

[xytech]

@ElizaD_Intel​  Hi could you help looke at this question, or help forward to relevant colleagues? Thanks!

[ShafiqY_Intel · Accepted solution]

Hi xytech,

Please refer to KDB below. I hope it will help you.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2017/can-i-use-2-5v-of-bank-1-vccio-for-as-configuration-with-epcqa-d.html

Thanks.

[xytech]

Hi MShafiq ,

Thanks very much for the link. It is indeed helpful.

Now we are forced to power Bank1 with 3.3V VCCIO and therefore True LVDS IOs on Bank1 are not available. We can only use Bank2/5/6 for True LVDS now. Also, power distribution network need to add one more 3.3V power supply, specially for Bank 1.

Although my questions are answered, I still do not understand why C10 LP AS config scheme can not support 2.5V VCCIO for bank1. At least , Cyclone IV suport this feature.

Further more, this is a strange featur that Bank1 support LVCMOS 2.5 I/O standard while can't support 2.5V flash interfacing on AS config mode. This whole limits the usage of io and this limitation do requires users to read and confirm it rather carefully. A ridiculous thing is , we consulted Cytech on this doubts, one of Altera's angency (also our supplier for Intel FPGA), their FAE just told me it may be OK to use 2.5V ofr bank1 on AS config and may be it's just Documentation Error to miss 2.5V !!! unbelievable.

By the way, I noticed a lot of EPCS and EPCQ products are End of Life or about to be terminated(as blew links). Cytech do not inform us.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pcn/pdn1708.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pcn/pdn1802.pdf