I use a CycloneII (EP2C5T144) as a global control of a high power electronics board, designed a few years ago.
Now there is notest on some boards that the FPGA "freezes" during operation. After a power cycle it works Ok for a time until it again freezes.
* Investigations done:
1) When "freezed":
All power rails OK.
All user IO seems to be at Tri-State/High-Z: IO-levels are in accordiance with the external Pull-Up or Pull-Down Ressistors.
Measured some extra signals:
ConfigDone: High-3V3
nConfig: High-3V3
nCE: Low-0V (Pull Down via 10K)
nStat: High-3V3
Clk: OK, 32Mc, 3V3
MSEL1,2: OK, 2b'10: Fast AS-Mode
Signals to EPSC1: all signals High-3V (3V ok??)
JTAG: FPGA reconized via JTAG (ref. "Auto Detect")
2) Try to "unfreeze":
Recycle the power of the total board: OK. FPGA running.
Loading the SOF-file via JTAG: no errors, still "freezes".
Pulling nConfig down: still "freezes".
3) At the molent the FPGA "Freezes":
Checked the voltage rails: OK, no dips, no overshoot.
* Extra Info:
EP2C5 is configures in ASmode with an EPCS1.
It's a power electronics board: so there can be expect some noise. If the FPGA freeses it is always when the board is at max load.
No use of any tri-state IO on the logic design.
No use of the nDEV_CLR and/or DEV_OE pins.
*Some tips?
Does someone an idea why the FPGA-IO goes to global Tri-State/High-Z?
Does someone hase some ideas about extra checks, measurements?
Thanks,
Kind Regards, SDPR
