DC couple connectivity of LVDS protocol between 1.8V to 2.5V

[Omerkv]

Hi

I would like to consult regarding the following issue:

Can LVDS protocol can work on a DC couple connectivity between two FPGA's where one FPGA the LVDS pins are connected to 1.8V IO standard /voltage level and the other one is connected to 2.5V IO standard /voltage level?

I suspect not, due to the contradiction between the voltage level and only ac couple connectivity can work at this state.

Regards

Omer

[FvM]

Wrong assumption, they are fully compatible. LVDS IO standard has 1.2 V common mode voltage independent of supply voltage.

[AqidAyman_Intel]

Hi Omer,

Yes, it is supported.

As mentioned, VCCIO is not related to the combability between two LVDS interface. As long as the required voltage (Vid,Vicm,Vod,Vocm) for both interface is met, then it can work.

You can refer to below link for the KDB article on this:

https://www.intel.com/content/www/us/en/support/programmable/articles/000074485.html?wapkw=1%208v%20lvds

Regards,

Aqid

[AqidAyman_Intel]

Hi Omer,

I wish to follow up with you on this question,

May I know if the answers provided so far helps you to move forward? If no, let us know for the continue of support.

Regards,

Aqid

[AqidAyman_Intel]

As we do not receive any response from you on the previous reply have been provided, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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