DDC Mixer Scale Block (https://www.intel.com/content/www/us/en/programmable/documentation/hco1423077212985.html#hco1423076748310)

[LMelo5]

Hi to all!.

Where can I find information on the ddc mixer scale block?

I would like to realize a ddc (digital down converter) with a 16 bit adc, a 16 bit nco a 16 * 16 multiplier (out 32).

Reading the intel docs I heard about a block that reduces the bits after the multiplier (in my case 32 bits), and does not cause significant information loss.

The docs speak of a module that executes shift-round-saturate operation.

Where can I find more information about its implementation?

Are there examples in vhdl?

Best regards, Luca.

[CheePin_C_Intel]

Hi,

Sorry for the delay. As I understand it, you are looking for the "DSP Builder DDC Design Example" as discussed in the DSP Builder for Intel FPGAs (Advanced Blockset): Handbook. For your information, this is an DSP Builder example design but not a specific IP block. To use the example design, you would need to installed compatible Matlab version and DSP Builder software for your Quartus. Note that you would require separate licenses for Matlab and DSP Builder softwares. After you installed DSP Builder, you would be able to find this example under the example design library.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

[LMelo5]

Tnx cpchan!

Which is the older version of quartus/dspbuilder that contains this example?

Is the Quartus 18.1 Standard sufficient?

[CheePin_C_Intel · Accepted solution]

Hi,

Based on my understanding, Q18.1Std should be sufficient. You can find it under dspba -> Examples -> Platforms -> demo_ddc.mdl in DSP builder.

Please let me know if there is any concern. Thank you.