DDIO Input Speed Cyclone V vs. Cyclone 10GX

[GLees]

When I create a simple DDIO input for both the Cyclone V and Cyclone 10GX parts, the Cyclone V has an Fmax about twice the Cyclone 10GX.

Cyclone V, Fmax ~ 400Mhz

Cyclone 10GX, Fmax < 200Mhz

I have attached archived projects for each.

[lixy]

Hi,

Since I still couldn't open the project you provided, I created a project with cyclone 10gx device to match your netlist.

I wonder if the IP you used in C10 GX project is "GPIO Intel FPGA IP"?

I used this IP in cyclone 10gx project and found that it is true that the Fmax is under 200MHz.

When Fmax Restricted = Fmax, it generally means that the speed is limited to the design instead of device.

In this case, it might be related to the IP itself.

Thanks & Regards,

XY

[GLees]

Thank you for taking the time to re-create the project and to verify my result, that Fmax < 200Mhz.  I used the "GPIO Intel FPGA IP" as you guessed.  What I don't understand is why the cyclone 10gx is so much slower than the cyclone 10 lp, or even the cyclone v.  I'm trying to design a 64 bit, DDR, source-synchronous deserializer with an input clock rate of at least 350Mhz.  The DDR input speed is key to my design and I can't seem to achieve it with what is supposed to be a high perfomance FPGA.

[AdzimZM_Intel]

Hi Greg,

I am Adzim from Global Application Engineer team will assist you in this issue.

I would like to have your confirmation here regarding to this issue.

The attachments are failed to open due to corrupted file. Can you re-attached it again?

You are using Cyclone 10 GX device and currently observing the fmax is lower than other devices. Which IP that you used for that observation?

Do you have any problem to configure the DDR IP? Do let me know if you have any.

Thanks & Regards,

Adzim

[GLees]

I am using GPIO Intel FPGA IP.  I have made a fresh archive of the project and have attached it.  Yes, the Fmax is lower than other devices and I have no problem configuring the IP.

Thanks,

Greg

[AdzimZM_Intel]

Hi Greg,

Thank you for your feedback.

FYI, the Fmax is only based on setup timing, while the Restricted Fmax is based on setup, hold and minimum period/pulse width timing.

The timing violation in the design will limit the Fmax and the Restricted Fmax.

If the design can get a clean timing, then the Fmax should be better.

If you cannot close the timing or the data rates are more than 200 Mbps, Intel recommends that you use the PHYLite for Parallel Interfaces IP core.

Regards,

Adzim

[GLees]

It seems odd, almost unbelievable, that the max data rate for the Cyclone 10GX is half the speed of the Cyclone 10LP and Cyclone V.  The PHYLite appears to utilize the GX transceivers and is very much overkill for my application.  I'm trying to design a 64 bit, DDR, source-synchronous deserializer with an input clock rate of 350Mhz.

[AdzimZM_Intel]

Hi Greg,

Why you do not use EMIF IP for Cyclone 10 GX device?

You can get higher data rate because it's a hard IP for DDR memory standard.

Regards,

Adzim

[GLees]

I guess due to my own ignorance.  I assumed "EMIF IP" was for external memory interfaces.  As I explained, I want to design a deserializer.  Is the EMIF IP general-purpose enough for me to use it for a deserializer?  I need 8 channels, 64 bits each, 350Mhz DDR clock.

[AdzimZM_Intel]

Hi Greg,

The EMIF interface required a lot of resources. This may not applicable to instantiate 8 interfaces in a design.

An Altera GPIO IP can support a maximum interface frequency of 300 MHz. This will limit the clock rate of the design.

This is the limitation of the IP itself.

Regards,

Adzim