DDIO Output Timing Errors on a Source Synchronous Interface (RGMII)

mriemleit · ‎09-24-2021

Hi Intel Community,

I've got problems with the timing of a RGMII Interface.

In my design the FPGA imitates an Ethernet PHY. So the FPGA has to delay the RX and TX clock by 90 degree internally.

The FPGA is the Arria10: "10AX027H4F343SG" and I'm using Quartus Pro 21.2.

The RX Path is working without any timing errors, but the TX Path doesn't.

I've worked through:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an477.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an433.pdf

The clocking structure is like Figure 15. of an433 with clock_out delayed by 90°.

As PLL Compensation mode I tried "Source Synchronous" and "Normal", both have nearly the same result.

My SDC File:

# Generate 125 MHz Clock
create_generated_clock -name RGMII125_TxClk -source [get_pins {inst_Rgmii1Slave|i_rgmiiPins|inst_rxPll|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]}] [get_pins {inst_Rgmii1Slave|i_rgmiiPins|inst_rxPll|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[1]}]

# Apply a generated clock to the clk_out port
create_generated_clock -name RGMII1Data_TxClk -source [get_pins {inst_Rgmii1Slave|i_rgmiiPins|inst_rxPll|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[2]}] [get_ports {pol_rgmii1_txClk}]

derive_clock_uncertainty

set t(maxDelay) 1.0
set t(minDelay) -1.0

# Set output delay based on the requirements mentioned previously
set_output_delay -clock RGMII1Data_TxClk -max $t(maxDelay) [get_ports pov_rgmii1*] -add_delay
set_output_delay -clock RGMII1Data_TxClk -min $t(minDelay) [get_ports pov_rgmii1*] -add_delay
set_output_delay -clock RGMII1Data_TxClk -clock_fall -max $t(maxDelay) [get_ports pov_rgmii1*] -add_delay
set_output_delay -clock RGMII1Data_TxClk -clock_fall -min $t(minDelay) [get_ports pov_rgmii1*] -add_delay
set_output_delay -clock RGMII1Data_TxClk -max $t(maxDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay
set_output_delay -clock RGMII1Data_TxClk -min $t(minDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay
set_output_delay -clock RGMII1Data_TxClk -clock_fall -max $t(maxDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay
set_output_delay -clock RGMII1Data_TxClk -clock_fall -min $t(minDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay

# Set false paths to remove irrelevant setup and hold analysis
set_false_path -fall_from [get_clocks RGMII125_TxClk] -rise_to [get_clocks RGMII1Data_TxClk] -setup
set_false_path -rise_from [get_clocks RGMII125_TxClk] -fall_to [get_clocks RGMII1Data_TxClk] -setup
set_false_path -fall_from [get_clocks RGMII125_TxClk] -fall_to [get_clocks RGMII1Data_TxClk] -hold
set_false_path -rise_from [get_clocks RGMII125_TxClk] -rise_to [get_clocks RGMII1Data_TxClk] -hold

set_false_path -to [get_ports {pol_rgmii1_txClk}]

The timing analysis looks like it takes the correct edges. But the timing is not so good...

Setup Violation:

Setup Waveform:

Hold Violation:

Hold Waveform:

Because setup and hold is violated I think I can't fix it with moving some edges. I have to improve something else in the design.

When I have a look in the "Resource Property View" I see that Quartus uses some weird DDIO component. Not the one that is included in the IO:

So I thought I can move it with the assignment:

set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to pov_rgmii*

or

set_instance_assignment -name FAST_OUTPUT_REGISTER_REGISTER ON -to pov_rgmii1_tx[0] -entity top

But Quartus just ignores it:

The IO-Standard is 1.8-V HSTL Class II and the Slew Rate is set to 1.

I'm out of ideas.... Maybe the FPGA isn't fast enough? But it's just 125 MHz with 8 ns Period and a valid window of 2 ns per data.

That can't be so hard. What am I doing wrong?

Thanks a lot for your help!

Best regards,

Michael

Ash_R_Intel · ‎09-26-2021

Hi,

Can you try with following constraint changes to the sdc?

1) Add create_clock constraint for the clk_in of the pll.

2) Add derive_pll_clocks

3) Remove create_generated_clock constraints as the derive_pll_clocks does the required job.

Regards

mriemleit · ‎09-28-2021

Hi Ash,

thanks for your time and help!

I added 1) and 2) => I've still the same problem.

3) I'm sorry but, I don't know what you mean.

I've an output clock (RGMII125_TxClk) and the 90° shifted clock that is set on the output pin (RGMII1Data_TxClk). How can I tell the timing analysis to analyse setup and hold time, related to the clock at the output pin when I don't name them?

The "create_generated_clock" statements are from page 10 of: an433.pdf

The names are quite bad, so I updated them in the .sdc file:

# create BaseClock
create_clock -name RGMII1_RxClk -period 125MHz [get_ports {pil_rgmii1_rxClk}]

# Generate 125 MHz Clock
create_generated_clock -name RGMIICLK_Data -source [get_pins {inst_Rgmii1Slave|i_rgmiiPins|inst_rxPll|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]}] [get_pins {inst_Rgmii1Slave|i_rgmiiPins|inst_rxPll|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[1]}]

# Apply a generated clock to the clk_out port
create_generated_clock -name RGMIICLK_Clk -source [get_pins {inst_Rgmii1Slave|i_rgmiiPins|inst_rxPll|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[2]}] [get_ports {pol_rgmii1_txClk}]

derive_pll_clocks -create_base_clocks
derive_clock_uncertainty

set t(maxDelay) 1.0
set t(minDelay) -1.0

# Set output delay based on the requirements mentioned previously
set_output_delay -clock RGMIICLK_Clk -max $t(maxDelay) [get_ports pov_rgmii1*] -add_delay
set_output_delay -clock RGMIICLK_Clk -min $t(minDelay) [get_ports pov_rgmii1*] -add_delay
set_output_delay -clock RGMIICLK_Clk -clock_fall -max $t(maxDelay) [get_ports pov_rgmii1*] -add_delay
set_output_delay -clock RGMIICLK_Clk -clock_fall -min $t(minDelay) [get_ports pov_rgmii1*] -add_delay
set_output_delay -clock RGMIICLK_Clk -max $t(maxDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay
set_output_delay -clock RGMIICLK_Clk -min $t(minDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay
set_output_delay -clock RGMIICLK_Clk -clock_fall -max $t(maxDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay
set_output_delay -clock RGMIICLK_Clk -clock_fall -min $t(minDelay) [get_ports {pol_rgmii1_txCtl}] -add_delay

# Set false paths to remove irrelevant setup and hold analysis
set_false_path -fall_from [get_clocks RGMIICLK_Data] -rise_to [get_clocks RGMIICLK_Clk] -setup
set_false_path -rise_from [get_clocks RGMIICLK_Data] -fall_to [get_clocks RGMIICLK_Clk] -setup
set_false_path -fall_from [get_clocks RGMIICLK_Data] -fall_to [get_clocks RGMIICLK_Clk] -hold
set_false_path -rise_from [get_clocks RGMIICLK_Data] -rise_to [get_clocks RGMIICLK_Clk] -hold

set_false_path -to [get_ports {pol_rgmii1_txClk}]

pnp · ‎09-29-2021

Edit: Sorry, I should have read more thoroughly--you're referencing timing violations, not a broken interface.

Best regards,

Paul

---

Hi,

I'm not sure if this relates to your issue, but I got recently got burned trying to apply that Application Note by the DDIO IP's port naming. It turned out my forwarded clock was inadvertently flipped 180 degrees, breaking my source synchronous interface:

https://community.intel.com/t5/FPGA-Intellectual-Property/GPIO-DDRIO-IP-output-swapped-datainhi-datainlo-inverts-forwarded/m-p/1317982#M24752

The documentation for that IP is not my favorite.

Ash_R_Intel · ‎10-05-2021

Hi,

Could you please share sample Quartus design files where we see the timing errors? This will help us in debugging it better.

You may remove other custom logic if you will.

Regards

mriemleit · ‎10-15-2021

Hi Ash,

here is the example project. I stripped everything except the RGMII Modul.

It would be great if you could point me in the right direction.

Many thanks in advance!

Best regards,

Michael

Ash_R_Intel · ‎02-16-2022

Sorry, that I could not spend enough time to this thread. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you