DDR input without DPA in Arria II GX

[Altera_Forum]

Hello 

 I am using arria ii gx to communicate with a high speed device. The device is sending DDR data, data with a data clock, dclk. dclk and data are source synchronous. I need to capture the data inside my Arria II GX FPGA, using dclk and separate it into a positive & negative edge streams.   The problem is that the skew between dclk and data, by the time they get into the FPGA, is unknown. Thus I want to be able to slide dclk or try different phases of dclk to capture the data. I was able to do this in Xilinx Virtex FPGAs using the iobdelay function, which allowed me to adjust the skew between dclk and data at run time. I want to do exactly the same in Arria II GX but I find no comparable option. I do not have a training pattern so the dpa is out. Can someone suggest a solution? Can I gain the ability to try various phases of dclk for sampling data in Arria II GX?  Thanks in advance for your help!!!

[Altera_Forum]

I used it in virtex iv .. here is an instantiation 

 IDELAY # (  .IOBDELAY_TYPE ("VARIABLE"),  .IOBDELAY_VALUE (`DQ_DEFAULT_DLY) )  IDLY_inst_[`data_width-1:0]  (  .O (idly_out[`data_width-1:0]),  .I (DDR_DQ[`data_width-1:0]), //ADC Data  .C (CLK),  .CE (dq_idelay_ce[`data_width-1:0]),  .INC (dq_idelay_inc[`data_width-1:0]),  .RST (dq_idelay_rst[`data_width-1:0])  );

[Altera_Forum]

Friends, 

 I have instantiated an external PLL whose output clocks drive an alt_lvds instance which has dpa enabled. I am slightly confused about the operation of this circuit; is the dpa going to generate 8 phases from its input clock (output of external PLL) and choose the best one? On top of dpa ckt generating its own 8 phases, I can also adjust the phase of PLL output clock by varying PLL settings?  Can I use "rx_dpll_enable" at run time to dynamcially enable/diable dpa circuitry? "rx_dpll_enable" is mentioned in Arria literature but not in Arria II GX literature.  Thanks for your guidance!

[Altera_Forum]

The PLL actually produces the 8 phases of clock. All the altlvds instance w/DPA does is select which one to use for sampling the input data. 

 Jake

[Altera_Forum]

--- Quote Start ---  Can I use "rx_dpll_enable" at run time to dynamcially enable/diable dpa circuitry?  --- Quote End ---  Unlike Arria I, Arria II GX hasn't a DPA bypass multiplexer. It can be configured either in non-DPA or DPA mode at compile time. As with Arria I, you can however freeze the current DPA phase by asserting rx_dpll_hold. This is necessary, when the DPA adjustment is done based on a train pattern, but the regular bitstream isn't guaranteed to have edges.

[Altera_Forum]

Friends, 

 I am trying to use the dpa with external PLL but I am getting the fitter warning and error  DPA clock of SERDES receiver atom "rx_0" is driven by PLL "PLL_NAME" with unspecified dpa_multiply_by and dpa_divide_by parameters  Error: The lvds clock and the DPA clock frequency of SERDES receiver atom "rx_0" must be the same  The following support for interfacing DPA to external PLL does not apply because I do not see the option of "Use these clock settings for dpa clock" in PLL/lvds generated for Arria II GX  http://www.altera.com/support/kdb/solutions/rd11212007_95.html  Thanks in advance for your help!

[Altera_Forum]

Friends, 

 fyi, I got rid of fitter errors with the help of following posts  http://www.altera.com/support/kdb/solutions/rd07142008_32.html http://www.altera.com/support/examples/functionality/pll-clocking-stratix3.html   - How would I "defparam" these dpa_divide_by and dpa_multiply_by when I dynamically configure my PLL through scan chain control; I do not know what entry in configuration .mif file corresponds to these parameter?   - I am never getting rx_dpa_locked asserted in my simulations, any idea why?  Regards,