Hi,
I am using the DDR2 SDRAM Controller with UNIPHY in qsys, I have instantiated the ddr controller instance in qsys and have generated the qsys. I am using VHDL.
The component declaration for the qsys has a dqs and dqs_n pin. I have created a dqs and dqs_n pin in my top level file. When I go to the pin planner and assign dqs it auto generates the dqs(n) pin and assigns it to the correct pin that is the other differential pair pin.
How should I connect this in my VHDL. Should I assign both of the component instance outputs to dqs? will quartus interpret this correctly? Or should I create both a dqs and dqs_n pin and assign them another way?
example:
ENTITY example IS
PORT
(
dqs : INOUT std_logic; --**these are the pins that I made to map to the qsys component outputs
dqs_n : INOUT std_logic
);
END ENTITY;
ARCHITECTURE eg OF example IS
--qsys component with ddr2
COMPONENT qsys_component IS
PORT
(
dqs : INOUT std_logic; --** these are created by the qsys component
dqs_n : INOUT std_logic
);
END COMPONENT;
BEGIN
--instance of qsys
example_instance : qsys_component
PORT MAP
(
dqs => dqs, --** is this correct?
dqs_n => dqs_n --** should this instead be dqs_n => dqs for the pin planner?
);
END ARCHITECTURE;
Thanks
James
