Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

DDR2 TimeQuest

Altera_Forum
Honored Contributor II
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Hi everybody! 

I am using the HPCII to control a DDR2 SDRAM with a cyclone III. When I compile the program, comes out the error "Critical Warning (332148): Timing requirements not met". In the time analysis I see a "bad" time slack for a clock generated from the pll of the controller.  

How could I fix this problem? 

 

thank you all
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