Hi Hi!!
I'am writing a sdc file for my_DDR2 Controller based on xxx_phy_ddr_timing.sdc file! This file comes with the Altera DDR2 Controller.
Can somebody tell me why the Altera guys set the max output_delay to (
1+tDQSS)*period + board_skew!! Where does the
1+ comes from???
from xxx_phy_ddr_timing.sdc:
set_output_delay -add_delay -clock $ckclock -max [round_3dp [expr {($off_tDQSS+1-$t(DQSS)) * $t(period) + $t(board_skew) + $fpga_tDQSS_SETUP_ERROR}]] $dqspin
info: Memory clock and DQS schould come at the same time at the MemoryChip. But DQS is allowed to be 25%period before or after the rising edge of clk!
tDQSS = DQS rising edge to Clk rising edge
tDQSSmin = -0.25*Clk_period (in all DDR2 memory datasheets) before clk
tDQSSmax = +0.25*Clk_period (in all DDR2 memory datasheets) after clk
thank's for your time!!
m
