DDR3 Testing

[Altera_Forum]

We are now about to test a new design with a DDR3. We are planning to first connect the DDR3 to our NIOS and do a full memory test of different addresses with differing values, most probably utilizing different banks. I doubt we will test the full depth of the memory. We are then to connect it to the NIOS instruction master and put our reset address there and run the NIOS code from there in conjunction with the NIOS instruction CACHE (note we do not currently use a a Data CACHE). 

Besides this basic memory test and then running our regular code from the DDR3, do you have any recommendations of a type of test that can fully test our design ?  Note: We will be soon acquiring a scope to check the signal integrity of the board and its DDR3.

[Altera_Forum]

Hi, 

You can make use of Altera EMIF example design for the testing: https://www.altera.com/documentation/hco1416493470528.html#hco1416493106997 The example design have a traffic generator component that will train the DDR3 read write and issue pass/fail flag after the rd/wr test.  (This message was posted on behalf of Intel Corporation)