DDR3 UniPHY Example Design simulation problem

[Alican]

I am trying to simulate my testbench based on DDR3 Example Design controller model.

Briefly; I use the DDR3 memory as dual port, under "Controller Settings" tab Number of ports:2. One of them is write-only 256 width, another is read-only and same width. After the generation IP, I can simulate burst read or burst write operations correctly. However, If I try to test read after write operation (for DDR3 standard: WRITE-ACTIVE-READ sequence), the ModelSim' s wave shows us "XXXX" on DQ port. When I have investigated the problem deeply, I have seen that memory controller block(altera model) try to drive the DQ port with previous WRITE data(!) while the operation is READ at that moment. My timing settings are correct according to standard and memory IC's datasheet.

Is there any known issue about this problem with simulation? Also, my design is working correctly on the real board.

Maybe, I couldn't construct appropriate testbench. 

[AdzimZM_Intel]

Hi Alican,

May I know which device and Quartus version that you're used?

Do you see any suspicious message in the transcript?

Thanks,

Adzim

[Alican]

Hi Sir,

My Quartus Version is 14.1 and my PLD is Cyclone-V that also called 5CGXFC9E6F31I7 part number. I tried to open debug messages as enabling verbosity bit on memory model and MagicWizard UI Option-1. But there are not any suspicious messages on the transcript. I can see CAS latency, reading data, writing data, writing or reading latencies according to memory model.

[AdzimZM_Intel]

Hi Alican,

Thank you for your reply.

I've tried to search for the known issue in the KDB website but I don't found the exact issue like your.

I've found a KDB that might be related to your issue.

Maybe you can try the workaround in the KDB. Link below.

https://www.intel.com/content/www/us/en/support/programmable/articles/000080439.html

Please let me know any update later.

I need to consult with the internal team for better understanding because I'm not familiar with this configuration.

I will let you know later.

Regards,

Adzim

[AdzimZM_Intel]

Hi Alican,

May I know any update on this topic?

Regards,

Adzim

[Alican]

Hi Sir,

I couldn' t find anything to fix this problem with UniPHY IP simulation model and DDR3 memory model. I disconnected whole path among the ddr3_cv_hard memory controller and  our controller block, then I developed my own Avalon-MM IP Simulation model and Memory model. After a challenging week, I got succeed. It still works well and faster than Intel' s models. Until Intel solve the problem, I consider to use my own model.

Regards,

Alican

[AdzimZM_Intel]

Hi Alican,

I think that you need to check the Avalon Write protocol.

It's might be some operations that are not done yet.

Here some documents that might help you. Avalon Interface Specification , Avalon Verification IP

But it's also an option for you to use your own memory controller in your design.

If it's working well and has a good performance, then you can use it.

The failure only occurs in the simulation right and your board is working as expected?

Regards,

Adzim

[Alican]

Hi again,

Thank you, I developed based on External Memory Interface Handbook from Altera and some simple reverse engineering via Questa Wave windows and some additional debug messages written by me. For example monitoring original flow; When do I have to read or drive the address, data, byte enable, etc ports of Avalon-MM... These helps me.

As a reply for your question, yes: It has worked on the real board since the beginning, It's only simulation problem. We used the Intel' s model a lot of times before but whole designs included only 1 port to read-or-write (as bidirectional). This was our first try to use dual port 1.=read, 2.=write only and then we struggled with the simulation problem. Finally the temporary solution has been found, but we hope that Intel solve this problem with any update or new Quartus version.

Regards,

Alican