Hello,
I am creating my own DDR3 controller. It is coming along well, but I have hit a few snags. My initialization up to and including the ZQ calibration is done. The issue then becomes trying to ensure that my write leveling and read calibration are correct. I have them both written, but I am not confident in them. Does anyone have any examples? The Jedec standard for DDR3 is free to download and is also on github. I have used the standards, but the write leveling is not very well written. I use VHDL and my chip is a DDR3-1600 one. My code is attached below.
Thank you,
Drew
