DDR3 accessing through SDRAM controller with Uniphy

[DGiar]

Hi everybody,

I need help about DDR3 accessing through SDRAM controller with Uniphy.

I use an Intel evaluation board ("Cyclone V E" dev kit).

I attach my qsys file.

I have two Avalon MM-masters connected to the Avalon MM-slave interface of the SDRAM controller: the first is the Nios, the second is a custom IP.

The problem seems to be in the "waitrequest_n" signal of the SDRAM controller MM-slave interface: when I connect only my custom IP everything works fine and the "waitrequest_n" signal is often '1' (as it should be, since the slave peripheral is "ready").

But when I connect both the Nios and the custom IP to the MM-slave interface, the "waitrequest_n" signal is '1' only for few time (and sometimes is stuck to '0'), even if the Nios is not communicating with the slave peripheral and the bus is busy only for the communication between my IP and SDRAM controller.

I attach also an oscilloscope screenshot with the "waitrequest_n" signal highlighted.

My questions are:

1) Is my design (at least in theory) correct? Or am I wrong in something?

2) I can only use the "soft memory controller" (because only this mode is supported by my dev kit). Is this a problem?

3) Both the MM-master peripherals run at the same clock frequency (150 MHz) but the clock network is not the same, since I cannot give to the Nios input clock the "afi_clk" of the SDRAM controller. Since I cannot modify the SDRAM Avalon slave clock (fixed to the "afi_clk" because of the "soft memory controller"), is there any smart idea to make all the peripherals run at the same clock? 

Thank you very much for your help.

[NurAida_A_Intel]

Hi DGiar,

I apologize for the delay in response. Please see my reply below:

My questions are:

1) Is my design (at least in theory) correct? Or am I wrong in something?

Ans: Everything seems OK. I don’t see any problem with your design. You are allowed to connect multiple master with one slave but please note that the efficiency will be slightly slow as you are sharing 2 master with one slave.

2) I can only use the "soft memory controller" (because only this mode is supported by my dev kit). Is this a problem?

Ans: No, it’s not the problem. But theoretically, hard memory is faster and have better efficiency than soft controller.

3) Both the MM-master peripherals run at the same clock frequency (150 MHz) but the clock network is not the same, since I cannot give to the Nios input clock the "afi_clk" of the SDRAM controller. Since I cannot modify the SDRAM Avalon slave clock (fixed to the "afi_clk" because of the "soft memory controller"), is there any smart idea to make all the peripherals run at the same clock?

Ans: I don’t understand why you unable to connect the afi_clk to the Nios. Supposedly can. You just need to connect the afi_clk to your Nios clock as shown below. Please correct me if I misunderstood your question.

Regarding the waitrequest_n signal, when you send instruction to your slave to perform read/write, at some moment the waitrequest_n signal will deassert for a while until the slave is ready to perform read/write again. Based on the oscilloscope screenshot, I can see the waitrequest_n signal is toggling correctly and I don’t see any stuck at 0 for too long.  

Thanks

Regards,

NAli1

[DGiar]

Hi,

after some weeks I managed to resolve this problem.

Now I'm able to communicate to the DDR memory from my custom IP component.

Thanks for your help!