DDR3 hard memory controller usage issue

[Altera_Forum]

Hello all I have implemented a hard memory controller on the Altera Cylcone V SOC development board. 

The board calibrates successfully but when I write some thing to address '0' and try to read it back, I only see zeros. Read data valid does go high though. I have attached signal tap screen caps. The first shows the write and read operation. The second shows read data valid going high but no valid data on readdata.  I have simulated the full design and it works correctly.  Any suggestions?  Thanks! https://alteraforum.com/forum/attachment.php?attachmentid=15830&stc=1  https://alteraforum.com/forum/attachment.php?attachmentid=15831&stc=1

[Altera_Forum]

Have you configured the Hard IP settings to correspond to that of the memory IC on the board from where you're writing and reading to? Have you set the CAS latency, RAS/CAS delay, etc? If the timing parameters are incorrect this can happen.

[Altera_Forum]

If the timing parameters are correct you can debug with the protocol checker. 

(Enable the EMIF toolkit debugging option and the efficiency monitor in the diagnostics tab of DDR3 controller settings) There is also an example design in QSYS available.

[Altera_Forum]

I believe I have set all the parameters correctly per the data sheet. 

There is a discrepancy though between the Development board reference manual and the memory data sheet. The reference manual states CL = 9, however for this chip running at 400 Mhz (2.5ns period) the memory data sheet states that CL = 6 and CWL = 5. I have tried it both ways with the same results.  The emif toolkit is not available for the Cyclone V SOC according to the External Memory Handbook. Is this not the case? IF the EMIF toolkit would work that would be great.   Does anyone know the correct settings for the Altera Cyclone V SOC development board? Here are the settings that I am using which I pulled from the memory data sheet. Memory part number Micron D9PXV  CL= 6 CWL = 5  tIS = 170 ps tIH = 120 ps tDS = 10 ps tDH = 45 ps tDQSQ = 100 ps tQH = 0.38 cycles tDQSCK 225 ps tDQSS = 0.27 cycles tQSH = 0.4 cycles tDSH = 0.18 cycles tINIT = 500 us tMRD = 4 cycles tRAS 35 ns tRCD = 15 ns tRP = 15 ns tREFI = 7.8 us tRFC 350 ns tWR 15 ns tWTR = 4 cycles tFAW = 40 ns tRRD = 10 ns tRTP = 10 ns   Thanks!

[Altera_Forum]

Just tried my VHDL interface code on a different development board which features the Cyclone V E, but the hard memory controller is not hooked up on that board.  

So using the same code but this time on the soft memory controller and everything works fine. So I do not believe I am doing anything wrong as far as interfacing with the controller.  The question then becomes why does the hard memory controller not respond the same way as the soft controller?