I can't configure the HPS DDR3 memory on a custom board with the Cyclone V SoC. The memory is IS43TR16512A-125KBLI. The preloader stops in the rw_mgr_mem_calibrate_read_test_patterns function with the following error:
SEQ.C: test_load_patterns(0,ALL) => (170 == 255) => 0
SEQ.C: Guaranteed read test failed: g=0 p=0 d=12
this means that after
IOWR_32DIRECT (RW_MGR_RUN_SINGLE_GROUP, ((group*RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS+vg) << 2), __RW_MGR_GUARANTEED_READ);
returns alternating sequence of ones and zeros instead of all zeros.
What can be the cause? How should I debug the problem?
There are 3 factor that I can think of that may cause DDR3 calibration failure - DDR3 IP setting issue, board design issue or preloader software build issue
My debug suggestion is as below.
- To isolate DDR3 IP setting and board design issue
- Generate DDR3 RTL example design using FPGA core DDR3 IP instead of HPS DDR3 IP
- Fix the pin location to match your existing SOC DDR3 pinout location
- If test fail then you need to debug further on either DDR3 IP setting or your board design
- If test pass then you can move on to debug preloader software build issue
- Debug preloader software build issue
- Checkout below golden reference design guideline to ensure you compile and build the preloader software correctly as per the guideline
Thank you for quick hints. I have followed the idea to separate the board/IP config/preloader compilation issue. However I have found that I can't map the FPGA SDRAM controller IP core signals to the HPS SDRAM controller pins in the pin planner. Is there any way to do this? Or should I use the FPGA to HPS SDRAM bridge? Which side is responsible for the configuration and calibration if I use the bridge, not the purely FPGA based controller?
Sorry, my mistake. Cyclone V FPGA HPS EMIF can't connect to normal FPGA GPIO. This can only be done with Arria 10 FPGA.
Your DDR3 calibration failed at guarantee read which is the first stage of calibration . So, most likely something fundamental is wrong here.
- This link may gives you some clue on what's the potential cause of calibration failure
For you case, you need to go back to basic to review your DDR3 IP setting and manually check board schematic again.
For DDR3 IP setting review - pls ensure the DDR3 IP setting matched with DDR3 SDRAM datasheet spec
For board schematic review - focus on DDR3 power and connection review. You can leverage attached schematic review worksheet - DDR3 section to find out the exact power pin and DDR3 pin connection that you need to check
Thank you for quick answers.
It is wrong fundamentally:/ After checking basic signal integrity I started looking at the command sequences and found that the DDR is not answering to any commands. Then I found that the RAS and CAS pins are swapped in the DDR schematic symbol:/
This would be very difficult to correct on the board and we may need to order corrected version as there is probably no option to swap these pins on the FPGA.
Please tell if there is any software trick to swap RAS/CAS pins (e.g. by FPGA lonaning, etc.). If there is no soft way, we will drill the board in a place where we can hit only the RAS and CAS lines and try to connect these on the through vias under the FPGA and DDR. This will affect signal integrity, but if we can run it at lower frequency we will be able to debug the board further before ordering the V1 version. Still there are some interfaces not checked, but this will be much easier if we can use the memory.
It's good that you found the root cause on the board but unfortunately HPS DDR3 IP comes with dedicated fixed pin connection. Therefore, you can't swap the RAS and CAS pin.
You can try rework your board as you mentioned or do a proper design respin on your board.
Thank you very much for your quick support.
Finally, by carefully analyzing the outer layer pattern to find the right position and using microscope to repeatedly check the drilling depth, I was able to drill 0.25mm hole and cut the wrong traces. They were cut close to the first DDR chip, so there are no stubs loading the line in the middle. Only some parts were left loading the FPGA output with undamped reflections. Next, I have connected vias under the FPGA and first DDR by a thin PTFE coax cable. Length was selected to match the PCB traces propagation. Shield was grounded to several vias close to the connection points.
Now it passes calibration and extensive tests @400MHz. So we can proceed with the V0 debugging before ordering next version.
It was a quite nasty mistake this time.