I've a project with a DDR3L SDRAM controller (quartus 15.1) , using a afi_half_clk = 350/2Mhz for the avalon the interface. The project is working, and if a compare a counter with a 125MHz and the afi_half_clk, the afi_half_clk counter is faster than the 125Mhz counter. But time quest reports that the afi_half_clk is equivalent to (350/4) Mhz (87.5).Please, can some one give me some idea to configure correctly the timequest constrains?
If you are using the memory controller IP, timing constraints are created for you automatically. You shouldn't have to change anything other than constraints for your own internal design. Which device are you using and are you sure you selected half-rate mode in the controller's IP Parameter Editor?
Thanks.I know that I don't have change the constreains files generated by the IP controller. It was just a way to ask for any idea/solution. We are using the FPGA 5CGTFD9E5F31C7. The IP controller is configured as enabled Hard ext. interface. The Avalon interface is confured as Full-rate, and enabled the Half-rate clock.
Hi,afi_half_clk depends on your controller configuration (Full-rate - or Half rate). On Full - rate controller afi_clk is half of the interface clock and afi_half_clk is interface clock/4
You see in Time Quest what you should see. As I said afi_half_clk depends on controller rate (Afi ratio). If you configured your controler as a Half-rate and 350MHz, then your afi_half_clk = 350/4 and Time Quest should report afi_half_clk = 87.5. If you want clock that is half of the interface use afi_clk not afi_half_clk.
I forgot to comment that, at the beginning, I tested the half_rate clock freq. using two counter; one with a 125MHz clock, and another with the half_rate clk.And the half_rate counter was faster than the 125MHz and equivalent (aprox) to 1/2 clk. So, I thought that the half_clk was 1/2 clock, instead of 1/4. Anyway I will repeat the test to confirm it.
I have just repeat the test. In this case, I have included 3 counters:1: with 125Mhz clock 2: with afi_half_rate clock 3: with afi_clk Comparing the counters 2 and 3 with counter 1, the results has been 2 -> 163MHz 3 -> 330Mhz
The problem is the order of the constraints file (SDC). The IP sdc file must be the last one.We had used the same order of a previous DDR2 projects, and we didn't detect it.