Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20753 Discussions

DDR4 calibration in Stratix 10 1SG040HH3F35E2LG device

David_S1
Beginner
627 Views

Hello,

We are using 1SG040HH3F35E2LG device in a custom board. We have generated an example design for DDR4(AS4C512M16D4) using traffic generator in Quartus Prime version 22.2. We have modified the DDR4 parameters according to our board design. The calibration got failed at the command/address deskew stage. The configuration details are as follows,

Memory format: Component

DQ: 64

PLL reference clock:133.333MHz 

memory clock frequency: 1066.667MHz

speed bin: 2133

Row address Width: 16

Column address width: 10

 

Please let me know for the corrective action.

 

Thanks,

David

 

0 Kudos
3 Replies
AdzimZM_Intel
Employee
598 Views

Hi David,


Can you check the design for any timing violation especially in Report DDR section?


Can you provided some snapshots of the EMIF Parameter Editor setting for checking the EMIF IP configuration?


Regards,

Adzim


0 Kudos
AdzimZM_Intel
Employee
544 Views

Hi David,


Is there any feedback to my previous comment?


Do you have any update in this thread?


Regards,

Adzim


0 Kudos
AdzimZM_Intel
Employee
505 Views

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


0 Kudos
Reply