HalloSo i have a DE0-NANO Board, and i tried to replace the on board oscillator with a external clock. I took out the on board oscillator and connected my external clock pin to pin 3 of the on board oscillator connection. I replaced the on board oscillator with a 22.5 MHz clock. Now the problem is when i try to synthesize the design i get a error at my top level clock module file. I dont use any pll and run my design with the same frequency as the external clock. I am attaching the vhdl file where it indicates and error and the error message is following Error (10518): VHDL type mismatch error at FPGA_top_clock_module.vhd(62): integer type does not match real literal File: FPGA_top_clock_module.vhd Line: 62 so the error points to line 62 and in line 62 it states that inclk0_input_frequency => 4.428855e+04,
so does this mean that i am only getting 44.2 KHz as my input clock to the FPGA????
You imply that by modifying your hardware you've broken your Quartus project. The question is what have you changed in your project? - assuming you had a project that synthesised before...Quartus doesn't need to know anything about the clock on the board if you're not using any PLLs. Cheers, Alex
I am not trying to imply anything here rather looking for a solution.So basically i generate my hdl code matlab hdl coder. DE0 NANO board is not directly recognized by MATLAB HDL coder, so you have to create a custom board where you specify the name of the board, clock pin (FPGA pin number as input clock), input clock frequency and in the interfaces you want to use for input and output from FPGA. So with the on board 50 MHz oscillator which is connected to pin R8 in the DE0 NANO board it was working fine. I could download the program to the board. So when i took out the oscillator and connected the external clock to the same FPGA pin, in the MATLAB HDL coder board definition instead of 50 MHz i just specified 22.5 MHz. And all the other settings including my simulink design file is same. And the error is explicitly referring to the clock module file, not to any of the vhdl files where my designs are so that's why i guessed that the external clock setting is wrong some how. And if you had a look at the attached vhd file, could you please tell me what does line 62 mean?
Line 62 is complaining because in the generic mapping section of the instantiation of component altpll (which means you are using a PLL) inclk0_input_frequency is defined as an integer type and 4.428855e+4 is a real.
thanks for the reply. So this means that some how MATLAB is creating a pll. And if i understood you correctly my input clock frequency is the value of inclk0_input_frequency and maltab is creating a pll out of it?
So matlab is generating your project and doing a bad job of it. It is instantiating a PLL which, as has been pointed out, is being configured incorrectly.In the interests of checking your hardware mod, restore the specified clock frequency (in matlab) back to what it was - 50MHz I presume - and see if that runs on your modified hardware. Whilst it may not work exactly as expected it should be sufficient to establish whether you've been successful in modifying your board. Then you can go about finding a work around for matlab's apparent blunder. You say "I dont use any pll ". Matlab clearly has. I think you need to start there. Cheers, Alex
hallo alexfirst of all sorry and thanks a lot. I thought i was running the fpga with the same external clock frequency, so i assumed matlab should not generate any pll, but it did actually generate a pll and created this problem. Which was pointed out in the earlier reply. I didn't quite clearly understand the part of putting the frequency back to 50 MHz and then checking, When i put the clock frequency back to 50 MHz it works, but how does it show that the board is working correctly? can you please explain.
Assuming your design makes use of the clock - and I assume it does given you're desire to change the clock source - then programming the "50MHz" design in, and seeing that it works, shows that your rework is good. Hence, the board is working correctly.So, now you have good hardware, complete with new clock source, you can concentrate on the FPGA design issues. Cheers, Alex
thanks, figured it out. It was actually an error form the MATLAB HDL coder side. The board is fine and now working with the new clock. But there are still some issues that needs to be solved on the fpga design but thats a different issue.just in case do u have any idea about a I2S slave receiver, i designed with simulink state flow and works fine in the simulation, but does not work when i download it on the fpga