DE2-115 "Working" Webserver built with Quartus 15.1

[Altera_Forum]

After 2 weeks of beating head against the wall, I finally got the board to get DHCP from my router and display the webpages correctly. 

Here is what I did to get it working in RGMII mode. The attached archive QAR project is setup for NET0 but if you want to use NET 1, just change the define in the top level verilog.  ATTACHED FILES 1) Attached is the archive of my project. It does not include the software but I did not make any changes from the original generated RGMII webserver. 2) Open up the archive in Quartus , compile and program the SOF to the DE2-115. Then, in your workspace, create a new project and bsp. Chose the webserver for RGMII and use the .sopcino file generated form Quartus. From there, everything should work fine with the names being correct.  CONVERSION 1) Quartus 12.1 is the last version that has both SOPC and QSYS together. I used 12.1 to convert the original files to a QSYS file. 2) I then opened up the project with Quartus 15.1 3) The old TSE does not work so I had to delete it and add in the new TSE 4) This is where my errors started, I had the wrong clock connections to the "receive_clock_connection" and "transmit_clock_connection". Originally I started with the actual tx and rx clocks going to the phy. I always got the code to run but the DHCP timed out everything. When I put these signals to the same clock as the CPU, everything came alive. The PCS clocks are the ones that need the phy clock. See the top level verilog for connections.  CODE CHANGES IN QSYS OR THE SOFTWARE 1) When you create your project the names in QSYS needs to match what is in the generated webserver software. I found it easier to change the names in QSYS . instead of "eth_mac" change it to "tse_mac" in qsys. change "cfi_flash" to "ext_flash". change "ledg" to "led_pio". By doing this in qsys, it will match the generated software of the webserver.  Why? The generated webserver code does not match what was in the original DE2-115 SOPC/QSYS. They need to match name for name.   2) The base address of the CFI flash MUST be at 0x0 in QSYS (we renamed it to ext_flash.) If you don't do this, the webserver can't find the HTML files written to flash. Set it to 0x0 and lock it down, then regenerate the address as needed. This is pointed out as a limitation in the readme file where the top level code was generated from the nios tools. Example /software/rgmii_webserver where i named my project rgmii_webserver.  Programming FLASH with ro_zipfs.zip 1) The webserver example looks forthis file at 0x100000. You can see this when you open up bsp_editor under "software packages". Use the flash programmer and set it up with the bsp you are using. when you pull in the ro_zipfs.zip file, you will see some scripts kick up. Modify the Files for flash conversion location to 0x100000 in the gui. It is under "Flash Offset" near the add and remove buttons.  Best of luck.  JC

[Altera_Forum]

Hi,  

 I would like to know the verion of Quartus 15.1 you use and also the kind of FPGA.  Indeed I try to follow your steps to realize this example but I can't make it work.   I do this with the Standard Edition of Quartus 15.1 and we are using as FPGA the Cyclone IV.  I ask this question because reading the file readme.txt edited when I build my project, it is written that something have to be change in the network_utilities.c with cyclone edition.  Thus, your help would be welcome.  BR