DE2 board USB communication

[Altera_Forum]

Hello people, 

I'm curious to know is there anyone who have experience with DE2 board USB communication ? There is some ISP1362 USB-OTG controller which must be appropriate configured in order to communicate with USB device plugged into DE2 USB connector. Does anybody worked with this controller using VHDL programming language ? Is there a lot of problem to configure ISP1362 USB-OTG controller ?  Thank you very much, Bojan

[Altera_Forum]

i'm trying to do DMA mode, that can read and write data, when buffer_full = '1' then it can start, my teacher said cannot use "wait until"... should i give you my whole code?

[Altera_Forum]

You need to write a clocked process and check the status of buffer_full. Don't use a while' use a if instead. If buffer_full is 0 then you don't do anything, if it is 1 then you start. 

If you need to do more complex operations after that, it could be easier to do with a state machine.

[Altera_Forum]

i know the clock process, but i dont know how to use it to check buffer_full. Can you explain more, thanks...

[Altera_Forum]

I assume that you are using tmp to detect a change in buffer_full ? 

In that case, in the clocked part put something like:if (tmp = '0') and (buffer_full = '1') then tmp <= '1'; -- do your start stuff here end if; Don't forget to give an initial value to tmp. And choose another name for tmp, to make your code more readable and maintainable. Something like 'active' or 'enabled' as an example.

[Altera_Forum]

i changed, but an new Error is appear... 

count := count + 1;  case count is  when 0 => NULL;  when 1 => word_buffer (03 downto 00) <= in_data;  when 2 => word_buffer (07 downto 04) <= in_data;  when 3 => word_buffer (11 downto 08) <= in_data;  when 4 => word_buffer (15 downto 12) <= in_data;  buffer_full <= '1';  bufferpicked: if tmp = '0' then buffer_picked <= '0';   elsif tmp = '1' then buffer_picked <= '1'; end if;   Error : slice that is assigned to target slice has 16 elements, but must have same number of element as target slice (4) Error: Can’t elaborate top-level user hierarchy

[Altera_Forum]

How big is in_data? The error message suggests that it is 16 bits, and you are trying to load it into 4 bits of another vector.

[Altera_Forum]

i change to when 1 => word_buffer (0011 downto 0000) <= in_data; 

when 2 => word_buffer (0111 downto 0100) <= in_data;  when 3 => word_buffer (1011 downto 1000) <= in_data;  when 4 => word_buffer (1111 downto 1100) <= in_data; but it said it is 12 elements, so confuzed, how to change? thank you

[Altera_Forum]

I think the vector indexes were right in your previous message. Constant integers in VHDL are expressed in decimal by default, not binary. 

 The problem must rather come from the fact that your input data vector in_data is 16 bits wide, and not 4.

[Altera_Forum]

Thank for your help, I correct all the errors and it can work lol^^... 

 But a new question is appeared, my teather said that the buffer_full cannot decided by the tmp, the program should check wether buffer_full is 0 or 1...  This buffer is decided by the DE2board, the PC or anything else??? I dont know checking where and how to check.

[Altera_Forum]

I don't have a DE2 board, but the answer should be in the kit and/or IP documentation.

[Altera_Forum]

hi 

i'm also communicating with PC-Altera DE2 by usb port... and i also don't want to use the Nios II.  It's possibile to see the vhdl code??

[Altera_Forum]

Hello Arun, The file DE2_NIOS_DEVICE_LED.sof is a programming file. Its a compiled version of the file which you have to program in your kid. Just connect your USB cable and select file in your programmer and program the device. After the programming the kit should start working until you reboot or reset.

[Altera_Forum]

--- Quote Start ---  Hi Koce,   to build up your USB communication you will have to configure your Philips ISP1362 USB-OTG controller from your VHDL code. Given that a simple Nios-II only takes a few procent of the Logic Elements on your DE2, it is probably the easiest to realize your USB communication via a Nios processor and using a JTAGUART.  --- Quote End ---    Hello,  I have developed the code that configures ISP1362 in pure VHDL. Please find the code here:  http://mzakharo.github.com/usb-de2-fpga/

[Altera_Forum]

--- Quote Start ---  Hello,  I have developed the code that configures ISP1362 in pure VHDL. Please find the code here:    --- Quote End ---    Salute to Mzakharo, I'm trying to migrate your code in my own design.